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freescale semiconductor data sheet: advance information document number: mcimx35sr2aec rev. 1, 12/2008 ? freescale semiconductor, inc., 2008. all rights reserved. preliminary?subject to change without notice this document contains information on a product under development. freescale reserves the right to change or discontinue this product without notice. mcimx35 package information plastic package case 5284 17 x 17 mm, 0.8 mm pitch ordering information see table 1 on page 3 for ordering information. 1 introduction the i.mx35 auto application processor family is designed for automotive infotainment and navigation applications. they are aecq100 grade 3 qualified and rated for ambient operating temperatures up to 85 c. the i.mx35 multimedia applications processor represents the next step in low-power, high-performance application processors. based on an arm11 microprocessor core running at up to 532 mhz, the device offers specific features and optimized system cost for the target applications. ? audio connectivity and telematics ? compressed audio playback from storage devices (cd, usb, hdd or sd card) ? playfromdevice (1-wire and 2-wire support) for portable media players ? ipod/iphone control and playback mcimx35 (i.mx35) multimedia applications processor for automotive products 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 functional description and application information . . . . . 5 2.1 application processor domain overview. . . . . . . . . 5 2.2 shared domain overview . . . . . . . . . . . . . . . . . . . . 6 2.3 advanced power management overview . . . . . . . . 6 2.4 arm11 microprocessor core . . . . . . . . . . . . . . . . . 6 2.5 module inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 signal descriptions: special function related pins . . . . 12 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 i.mx35 chip-level conditions . . . . . . . . . . . . . . . . 12 4.2 power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 supply power-up/power-down requirements and restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 thermal characteristics. . . . . . . . . . . . . . . . . . . . . 17 4.5 i/o pad dc electrical characteristics . . . . . . . . . . 17 4.6 i/o pad ac electrical characteristics . . . . . . . . . . 22 4.7 module-level ac electrical specifications. . . . . . . 28 5 package information and pinout . . . . . . . . . . . . . . . . . . 128 5.1 mapbga production package 1568-01, 17 x 17 mm, 0.8 pitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.2 production package outline drawing . . . . . . . . . 129 6 product documentation. . . . . . . . . . . . . . . . . . . . . . . . . 136 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 2 ? high-speed cd ripping to usb, sd/mmc or hdd for virtual cd changer ? audio processing for hands-free telephony: blue tooth, aec/ns, microphone beam forming, and so on. ? speech recognition ? a/v connectivity and navigation ? includes audio connectivity and telematics features ? map display & route calculation ? qvga video decode, wvga video display ? sophisticated graphical user interface the i.mx35 processor takes advantage of the arm1136jf-s? core running at 532 mhz that is boosted by a multi-level cache system, and features peripheral devices such as an autonomous image processing unit, a vector floating point (vfp11) co-processor, and a risc-based dma controller. the i.mx35 supports connections to various types of external memories, such as sdram, mobile ddr and ddr2, slc and mlc nand flash, nor flash and sram. the device can be connected to a variety of external devices such as high-speed usb2.0 otg, ata, mmc/sdio, and compact flash. 1.1 features the i.mx35 is designed for automotive infotainment video-enabled applications. the i.mx35 provides low-power solutions for high-performance de manding multimedia and graphics applications. the mcimx35 is based on the arm1136 platform, which has the following features: ? arm1136jf-s processor ? 16-kbyte l1 instruction cache ? 16-kbyte l1 data cache ? 128-kbyte l2 cache ? 128 kbytes of internal sram ? vector floating point unit (vfp11) to boost multimedia performance, the following hardware accelerators are integrated: ? image processing unit (ipu) ? openvg 1.1 graphics processing unit (gpu) (not available for the mcimx351) the mcimx35 provides the following interfaces to external devices (some of them are muxed and not available simultaneously): ? 2 controller area network (can) interfaces ? 2 sdio/mmc interfaces, 1 sdio/ce-ata interface (ce-ata is not available for the mcimx351) ? 32-bit mobile ddr, ddr2 (4-bank architecture), and sdram (up to 133 mhz) ? 2 configurable serial peripheral interfaces (cspi) (up to 52 mbps each) ? enhanced serial audio interface (esai) ? 2 synchronous serial interfaces (ssi)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 3 ? ethernet mac 10/100 mbps ? 1 usb 2.0 host with ulpi interface or internal full-speed phy. up to 480mbps if external hs phy is used. ? 1 usb 2.0 otg (up to 480 mbps) controller with internal high-speed otg phy ? flash controller?mlc/slc nand and nor ? gpio with interrupt capabilities ?3 i 2 c modules (up to 400 kbytes each) ?jtag ? key pad port ? media local bus (mlb) interface ? asynchronous sample rate converter (asrc) ?1-wire ? parallel camera sensor (4/8/10/16-bit data port for video color models: ycc, yuv, 30 mpixels/s) ? parallel display (primary up to 24-bit, 1024 x 1024) ? parallel ata (up to 66 mbytes) ?pwm ? spdif transceiver ? 3 uart (up to 4.0 mbps each) 1.2 ordering information table 1 provides the ordering information for the i.mx35 processor. table 1. ordering information description part number silicon revision type package 1 1 case 5284 is rohs-compliant, lead-free, msl = 3, 1. see application note an330 for details. speed operating temperature range ( c) i.mx351 mcimx351avm4b 2.0 automotive 5284 400 mhz -40 to 85 i.mx351 MCIMX351AVM5B 2.0 automotive 5284 532 mhz -40 to 85 i.mx355 mcimx355avm4b 2.0 automotive 5284 400 mhz -40 to 85 i.mx355 mcimx355avm5b 2.0 automotive 5284 532 mhz -40 to 85 i.mx356 mcimx356avm4b 2.0 automotive 5284 400 mhz -40 to 85 i.mx356 mcimx356avm5b 2.0 automotive 5284 532 mhz -40 to 85
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 4 table 2 shows the functional differences between the different parts in the i.mx35 family. table 2. part descriptions module mcimx351 mcimx355 mcimx356 i2c (3) yes yes yes cspi (2) yes yes yes ssi/i2s (2) yes yes yes esai yes yes yes spdif i/o yes yes yes usb hs host yes yes yes usb otg yes yes yes flexcan (2) yes yes yes mlb yes yes yes ethernet yes yes yes 1-wire yes yes yes kpp yes yes yes sdio/mmc (2) yes yes yes sdio/memory stick yes yes yes external memory controller (emc) yes yes yes jtag yes yes yes pata ?yesyes ce-ata ?yesyes image processing unit (ipu) (inversion and rotation, pre- and post-processing, camera interface, blending, display controller) ?yesyes open vg graphics acceleration (gpu) ? ? yes
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 5 1.3 block diagram figure 1 shows the i.mx35 simplified interface block diagram. figure 1. i.mx35 simplified interface block diagram 2 functional description and application information the mcimx35 consists of the following major subsystems: ? arm1136 platform?ap domain ? sdma platform and emi?shared domain 2.1 application processor domain overview the applications processor (ap) and its domain are responsible for running the operating system and applications software, providing the user interface, and supplying access to integrated and external peripherals. the ap domain is built around an arm1136jf-s core with 16-kbyte instruction and 16-kbyte data l1 caches, an mmu, a 128-kbyte l2 cach e, a multiported crossbar switch, and advanced debug and trace interfaces. external memory interface (emi) smart dma peripherals arm11 internal memory ddr2/sddr ram nor flash/ nand flash audio/power management arm1136jf-s esai spba cspi uart camera image processing unit (ipu) platform bluetooth mmc/sdio keypad vfp l2 cache max aips (2) jtag lcd display 2 lcd display 1 sensor external graphics accelerator timers gpt rtc gpio(3) wdog owire i2c(3) pwm kpp uart(2) 3 fusebox psram or wlan scc can(2) spdif hs usbotg ata iim cspi rticv3 esdhc(3) mshc asrc audmux l1 i/d cache etm av i c rngc epit ect iomux mlb fec hs usbotgphy hs usbhost fs usbphy ssi ssi gpio(3) ect gpu 2d connectivity access arm1136 platform peripherals
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 6 the arm11 core is intended to operate at a ma ximum frequency of 532 mhz to support the required multimedia use cases. furthermore, an image processi ng unit (ipu) is integrated into the ap domain to offload the arm11 core from performing functions such as color space conversion, image rotation and scaling, graphics overlay, and pre- and post-processing. peripheral functionality belonging to the ap domain in clude the user interface, connectivity, display, security, and memory interfaces and 128 kbytes of multipurpose sram. 2.2 shared domain overview the shared domain is composed of the shared pe ripherals, a smart dma engine (sdma) and a number of miscellaneous modules. for maximum flexibility, some peripherals are directly accessible by the sdma engine. the mcimx35 has a hierarchical memory architecture including l1 caches and unified l2 cache. this reduces the bandwidth demands for the external bus and external memory. the external memory subsystem supports a flexible external memory system, including support for sdram (sdr, ddr2 and mobile ddr) and nand flash. 2.3 advanced power management overview to address the continuing need to reduce power cons umption, the following techniques are incorporated in the mcimx35: ? clock gating ? power gating ? power optimized synthesis ? well biasing the insertion of gating into the clock paths allows unused portions of the chip to be disabled. since static cmos logic consumes only leakage power, si gnificant power savings can be realized. ?well biasing? is applying a voltage that is gr eater than vdd to the nwells and lower than v ss to the pwells. the effect of applying this well back bias voltage re duces the subthreshold channel leakage. for the 90-nm digital process, it is estimated that the subthreshold leakage is reduced by a factor of ten over the nominal leakage. additionally, the supply voltage for internal logic can be reduced from 1.4 v to 1.22 v. 2.4 arm11 microprocessor core the cpu of the i.mx35 is the arm1136jf-s core, based on the arm v6 architecture. this core supports the arm thumb ? instruction sets, features jazelle ? technology (which enables direct execution of java byte codes), and a range of simd dsp instructions th at operate on 16-bit or 8-bit data values in 32-bit registers. the arm1136jf-s processor core features are as follows: ? integer unit with integral embeddedice ? logic ? eight-stage pipeline ? branch prediction with return stack
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 7 ? low-interrupt latency ? instruction and data memory ma nagement units (mmus), managed using micro tlb structures backed by a unified main tlb ? instruction and data l1 caches, including a non-blocking data cache with hit-under-miss ? virtually indexed/physically addressed l1 caches ? 64-bit interface to both l1 caches ? write buffer (bypassable) ? high-speed advanced micro bus architecture (amba) ? l2 interface ? vector floating point co-processor (vfp) for 3d graphics and other floating-point applications? hardware acceleration ?etm ? and jtag-based debug support table 3 summarizes information about the i.mx35 core. 2.5 module inventory table 4 shows an alphabetical listing of the modules in the mcimx35. for extended descriptions of the modules, see the mcimx35 reference manual. table 3. i.mx35 core core acronym core name brief description integrated memory includes arm11 or arm1136 arm1136 platform the arm1136? platform consists of the arm1136jf-s core, the etm real-time debug modules, a 6 x 5 multi-layer ahb crossbar switch (max), and a vector floating processor (vfp). the i.mx35 provides a high-performance arm11 microprocessor core and highly integrated system functions. the arm application processor (ap) and other subsystems address the needs of the personal, wireless, and portable product market with integrated peripherals, advanced processor core, and power management capabilities. ? 16-kbyte instruction cache ? 16-kbyte data cache ? 128-kbyte l2 cache ? 32-kbyte rom ? 128-kbyte ram table 4. digital and analog modules block mnemonic block name domain 1 subsystem brief description 1-wire 1-wire interface arm arm1136 platform peripherals 1-wire provides the communication line to a 1-kbit add-only memory. the interface can send or receive 1 bit at a time. asrc asynchronous sample rate converter sdma connectivity peripherals the asrc is designed to convert the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. it supports a concurrent sample rate conversion of about ?120db thd+n. the sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. ata ata module sdma connectivity peripherals the ata block is an at attachment host interface. its main use is to interface with ide hard disk drives and atapi optical disk drives. it interfaces with the ata device over a number of ata signals.
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 8 audmux digital audio mux arm multimedia peripherals the audmux is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (ssis) and peripheral serial interfaces (audio codecs). the audmux has two sets of interfaces: internal ports to on-chip peripherals and external ports to off-chip audio devices. data is routed by configuring the appropriate internal and external ports. can(2) can module arm connectivity peripherals the can protocol is primarily designed to be used as a vehicle serial data bus running at 1 mbps. ccm clock control module arm clocks this block generates all clocks for the peripherals in the sdma platform. the ccm also manages arm1136 platform low-power modes (wait, stop), disabling peripheral clocks appropriately for power conservation, and provides alternate clock sources for the arm1136 and sdma platforms. cspi(2) configurable serial peripheral interface sdma, arm connectivity peripherals this module is a serial interface equipped with data fifos (first in first out); each master/slave-configurable spi module is capable of interfacing to both serial port interface master and slave devices. the cspi ready (spi_rdy) and slave select (ss) control signals enable fast data communication with fewer software interrupts. ect embedded cross trigger sdma, arm debug ect (embedded cross trigger) is an ip for real-time debug purposes. it is a programmable matrix allowing several subsystems to interact with each other. ect receives signals required for debugging purposes (from cores, peripherals, buses, external inputs, and so on) and propagates them (propagation programmed through software) to the different debug resources available within the soc. emi external memory interface sdma external memory interface the emi module provides access to external memory for the arm and other masters. it is composed of the following main submodules: m3if?provides arbitration between multiple masters requesting access to the external memory. sdram ctrl?interfaces to mddr, ddr2 (4-bank architecture type), and sdr interfaces. nandfc?provides an interface to nand flash memories. weim?interfaces to nor flash and psram. epit(2) enhanced periodic interrupt timer arm timer peripherals each epit is a 32-bit ?set-and-forget? timer that starts counting after the epit is enabled by software. it is capable of providing precise interrupts at regular intervals with minimal processor intervention. it has a 12-bit prescaler to adjust the input clock frequency to the required time setting for the interrupts, and the counter value can be programmed on the fly. esai enhanced serial audio interface sdma connectivity peripherals the enhanced serial audio interface (esai) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, spdif transceivers, and other dsps. the esai consists of independent transmitter and receiver sections, each section with its own clock generator. table 4. digital and analog modules (continued) block mnemonic block name domain 1 subsystem brief description
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 9 esdhcv2 (3) enhanced secure digital host controller arm connectivity peripherals the esdhcv2 consists of four main modules: ce-ata, mmc, sd and sdio. ce-ata is a hard drive interface that is optimized for embedded applications of storage. the multi-media card (mmc) is a universal, low-cost, data storage and communication media to applications such as electronic toys, organizers, pdas, and smart phones. the secure digital (sd) card is an evolution of mmc and is specifically designed to meet the security, capacity, performance, and environment requirements inherent in emerging audio and video consumer electronic devices. sd cards are categorized into memory and i/o. a memory card enables a copyright protection mechanism that complies with the sdmi security standard. sdio cards provide high-speed data i/o (such as wireless lan via sdio interface) with low power consumption. note: ce-ata is not available for the mcimx351. fec ethernet sdma connectivity peripherals the ethernet media access controller (mac) is designed to support both 10 and 100 mbps ethernet/ieee 802.3 networks. an external transceiver interface and transceiver function are required to complete the interface to the media gpio(3) general purpose i/o modules arm pins used for general purpose input/output to external ics. each gpio module supports 32 bits of i/o. gpt general purpose timers arm timer peripherals each gpt is a 32-bit free-running or set-and-forget mode timer with a programmable prescaler and compare and capture registers. a timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. when the timer is configured to operate in set-and-forget mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. the counter has output compare logic to provide the status and interrupt at comparison. this timer can be configured to run either on an external clock or on an internal clock. gpu2d graphics processing unit 2dv1 arm multimedia peripherals this module accelerates openvg and gdi graphics. note: not available for the mcimx351. i 2 c(3) i 2 c module arm arm1136 platform peripherals inter-integrated circuit (i 2 c) is an industry-standard, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. i 2 c is suitable for applications requiring occasional communications over a short distance among many devices. the interface operates at up to 100 kbps with maximum bus loading and timing. the i 2 c system is a true multiple-master bus, with arbitration and collision detection that prevent data corruption if multiple devices attempt to control the bus simultaneously. this feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer. table 4. digital and analog modules (continued) block mnemonic block name domain 1 subsystem brief description
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 10 iim ic identification module arm security modules the iim provides the primary user-visible mechanism for interfacing with on-chip fuse elements. among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, and various control signals requiring a fixed value. iomux external signals and pin multiplexing arm pins each i/o multiplexer provides a flexible, scalable multiplexing solution with the following features: up to eight output sources multiplexed per pin up to four destinations for each input pin unselected input paths held at constant levels for reduced power consumption ipuv1 image processing unit arm multimedia peripherals the ipu supports video and graphics processing functions. it also provides the interface for image sensors and displays. the ipu performs the following main functions: preprocessing of data from the sensor or from the external system memory postprocessing of data from the external system memory post-filtering of data from the system memory with support of the mpeg-4 (both deblocking and deringing) and h.264 post-filtering algorithms displaying video and graphics on a synchronous (dumb or memory-less) display displaying video and graphics on an asynchronous (smart) display transferring data between ipu sub-modules and to/from the system memory with flexible pixel reformatting kpp keypad port arm connectivity peripherals can be used for either keypad matrix scanning or general purpose i/o. mlb media local bus arm connectivity peripherals the mlb is designed to interface to an automotive most ring. oscaud osc audio reference oscillator analog clock the oscaudio oscillator provides a stable frequency reference for the plls. this oscillator is designed to work in conjunction with an external 24.576-mhz crystal. osc24m osc24m?24- mhz reference oscillator analog clock the signal from the external 24-mhz crystal is the source of the clk24m signal fed into usb phy as the reference clock and to the real time clock (rtc). mpll ppll digital phase-locked loops sdma clocks dplls are used to generate the clocks: mcu pll (mpll)?programmable peripheral pll (ppll)?programmable pwm pulse-width modulator arm arm1136 platform peripherals the pulse-width modulator (pwm) is optimized to generate sound from stored sample audio images; it can also generate tones. rtc real-time clock arm clocks provides the arm1136 platform with a clock function (days, hours, minutes, seconds) and includes alarm, sampling timer, and minute stopwatch capabilities. table 4. digital and analog modules (continued) block mnemonic block name domain 1 subsystem brief description
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 11 sdma smart dma engine sdma system controls the sdma provides dma capabilities inside the processor. it is a shared module that implements 32 dma channels and has an interface to connect to the arm1136 platform subsystem, emi interface, and the peripherals. sjc secure jtag controller arm pins the secure jtag controller (sjc) provides debug and test control with maximum security. spba sdma peripheral bus arbiter sdma system controls the spba controls access to the sdma peripherals. it supports shared peripheral ownership and access rights to an owned peripheral. s/pdif serial audio interface sdma connectivity peripherals sony/philips digital transceiver interface ssi(2) synchronous serial interface sdma, arm(2) connectivity peripherals the ssi is a full-duplex serial port that allows the processor connected to it to communicate with a variety of serial protocols, including the freescale semiconductor spi standard and the i 2 c sound (i 2 s) bus standard. the ssis interface to the audmux for flexible audio routing. uart(3) universal asynchronous receiver/trans mitters arm(ua rt1,2) sdma(u art3) connectivity peripherals each uart provides serial communication capability with external devices through an rs-232 cable using the standard rs-232 non-return-to-zero (nrz) encoding format. each module transmits and receives characters containing either 7 or 8 bits (program-selectable). each uart can also provide low-speed irda compatibility through the use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared led (for transmission). usboh high-speed usb on-the-go sdma connectivity peripherals the usb module provides high performance usb on-the-go (otg) functionality (up to 480 mbps), compliant with the usb 2.0 specification, the otg supplement, and the ulpi 1.0 low pin count specification. the module has dma capabilities handling data transfer between internal buffers and system memory. wdog watchdog modules arm timer peripherals each module protects against system failures by providing a method of escaping from unexpected events or programming errors. once activated, the timer must be serviced by software on a periodic basis. if servicing does not take place, the watchdog times out and then either asserts a system reset signal or an interrupt request signal, depending on the software configuration. 1 arm = arm1136 platform, sdma = sdma platform table 4. digital and analog modules (continued) block mnemonic block name domain 1 subsystem brief description
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 12 3 signal descriptions: special function related pins some special functional requirements are supported in the mcimx35 device. the details about these special functions and the corresponding pad names are listed in table 5 . 4 electrical characteristics the following sections provide the device-level and m odule-level electrical characteristics for the i.mx35 processor. 4.1 i.mx35 chip-level conditions this section provides the device-level electrical characteristics for the ic. see table 6 for a quick reference to the individual tables and sections. table 5. special function related pins function name pad name mux mode detailed description external arm clock ext_armclk alt0 external clock input for arm clock. external peripheral clock i2c1_clk alt6 external peripheral clock source. external 32-khz clock capture alt4 external clock input of 32 khz, used when the internal 24m oscillator is powered off, which could be configured either from capture or cspi1_ss1. cspi1_ss1 alt2 clock out clko alt0 clock-out pin from ccm, clock source is controllable and can also be used for debug. power ready gpio1_0 alt1 pmic power-ready signal, which can be configured either from gpio1_0 or tx1. tx1 alt1 tamper detect gpio1_1 alt6 tamper-detect logic is used to issue a security violation. this logic is activated if the tamper-detect input is asserted. tamper-detect logic is enabled by the bit of iomuxc_gpra[2]. after enabling the logic, it is impossible to disable it until the next reset. table 6. i.mx35 chip-level conditions characteristics table / location absolute maximum ratings table 7 on page 13 mcimx35 operating ranges table 8 on page 13 interface frequency table 9 on page 14
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 13 caution stresses beyond those listed in table 7, "absolute maximum ratings," on page 13 may cause permanent damage to the device. these are stress ratings only. functional operation of the devi ce at these or any other conditions beyond those indicated in table 8, "mcimx35 operating ranges," on page 13 is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4.1.1 mcimx35 operating ranges table 8 provides the recommended operating ranges. the term nvcc in this section refers to the associated supply rail of an input or output. table 7. absolute maximum ratings parameter symbol min. max. units supply voltage (core) vdd max 1 1 vdd is also known as qvcc. ?0.5 1.47 v supply voltage (i/o) nvcc max ?0.5 3.6 v input voltage range v imax ?0.5 3.6 v storage temperature t storage ?40 125 o c esd damage immunity: v esd v human body model (hbm) ? 2000 2 2 hbm esd classification level according to the aec-q100-002 standard. machine model (mm) ? 200 charge device model (cdm) ? 500 3 3 corner pins max. 750 v. table 8. mcimx35 operating ranges symbol parameter min. typical max. units vdd core operating voltage 0 < f arm < 400 mhz 1.22 ? 1.47 v core operating voltage 0 < f arm < 532mhz 1.33 ? 1.47 v state retention voltage 1 ? ? v nvcc_emi1,2,3 emi 1 1.7 ? 3.6 v nvcc_crm wtdg, timer, ccm, gpio, cspi1 1.75 ? 3.6 v nvcc_nandf nandf 1.75 ? 3.6 v nvcc_ata ata, usb generic 1.75 ? 3.6 v nvcc_sdio esdhc1 1.75 ? 3.6 v nvcc_csi csi, sdio2 1.75 ? 3.6 v nvcc_jtag jtag 1.75 ? 3.6 v
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 14 4.1.2 interface frequency limits table 9 provides information on interface frequency limits. nvcc_lcdc lcdc, ttm, i2c1 1.75 ?3.6 v nvcc_misc i2sx2,esai, i2c2, uart2, uart1, fec 1.75 ? 3.6 v nvcc_mlb 2 mlb 1.75 ? 3.6 v phy1_vdda usb otg phy 3.17 3.3 3.43 v usbphy1_vdda_bias usb otg phy 3.17 3.3 3.43 v usbphy1_upllvdd usb otg phy 3.17 3.3 3.43 v phy2_vdd usb host phy 3.0 3.3 3.6 v osc24m_vdd osc24m 3.0 3.3 3.6 v osc_audio_vdd osc_audio 3.0 3.3 3.6 v mvdd mpll 1.4 ? 1.65 v pvdd ppll 1.4 ? 1.65 v fuse_vdd 3 fusebox program supply voltage 3.0 3.6 3.6 v t a operating ambient temperature range ?40 ? 85 o c t j junction temperature range ?40 ? 105 o c 1 emi i/o interface power supply should be set up according to external memory. for example, if using sdram then nvcc_emi1,2,3 should all be set at 3.3 v (typ.). if using mddr or ddr2, nvc_emi1,2,3 must be set at 1.8 v (typ.). 2 mlb interface i/o pads can be programmed to function as gpio by setting nvcc_mlb to 1.8 or 3.3 v, but if used as mlb pads, nvcc_mlb must be set to 2.5 v in order to be compliant with external most devices. nvcc_mlb may be left floating. 3 the fusebox read supply is connected to supply of the full speed usbphy. fuse_vdd is only used for programming. it is recommended that fuse_vdd be connected to ground when not being used for programming. table 9. interface frequency id parameter symbol min. typ. max. units 1 jtag tck frequency f jtag dc 5 10 mhz table 8. mcimx35 operating ranges (continued) symbol parameter min. typical max. units
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 15 4.2 power modes table 10 provides descriptions of the power modes of the mcimx35 processor. table 10. mcimx35 power modes power mode description qvcc(arm/l2 peripheral) mvdd/pvdd osc24m_vdd osc_audo_vdd typ. max. typ. max. typ. max. wait qvcc1,2,3,4 = 1.1 v (min.) arm is in wait for interrupt mode. max is active. l2 cache is kept powered. mcu pll is on (400 mhz) per pll is off (can be configured) (default: 300 mhz) module clocks are gated off (can be configured by cgr register). osc 24m is on. osc audio is off (can be configured). .rngc internal osc is off tbd tbd tbd tbd tbd tbd doze qvcc1,2,3,4 = 1.1v (min.) arm is in wait for interrupt mode. max is halted. l2 cache is kept powered. l2 cache control logic off. awb enabled. mcu pll is on(400 mhz) per pll is off (can be configured). (300mhz). module clocks are gated off (can be configured by cgr register). osc 24m is on. osc audio is off (can be configured) .rngc internal osc is off tbd tbd tbd tbd tbd tbd stop qvcc1,2,3,4 = 1.1v (min.) .arm is in wait for interrupt mode. .max is halted .l2 cache is kept powered. .l2 cache control logic off. .awb enabled. .mcu pll is off. .per pll is off. .all clocks are gated off. .osc 24mhz is on .osc audio is off .rngc internal osc is off 790 a tbd 40 a tbd 1 ma tbd
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 16 4.3 supply power-up/power-down requirements and restrictions any i.mx35 board design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operati on of the device. any deviation from these sequences can result in any or all of the following situations: ? excessive current during power-up phase ? prevent the device from booting ? irreversible damage to the i.mx35 processor (worst-case scenario) 4.3.1 powering up the power-up sequence should be completed as follows: 1. assert power on reset (por ). 2. turn on digital logic domain and i/o power supplies vdd n and nvcc x. 3. wait 32 s. 4. turn on all other analog power supplies, including phy1_vdda, usbphy1_vdda_bias, phy2_vdd, usbphy1_upllvdd, osc24m_vdd, osc_audio_vdd, mvdd, pvdd, and fusevdd (fusevdd is tied to gnd if fuses are not being programmed). 5. wait 100 s. 6. negate the por signal. static qvcc1,2,3,4 = 1.0v .arm is in wait for interrupt mode. .max is halted .l2 cache is kept powered. .l2 cache control logic off. .awb enabled. .mcu pll is off. .per pll is off. .all clocks are gated off. .osc 24mhz is off .osc audio is off .rngc internal osc is off 770 a tbd 50 a tbd 26 a tbd note: typical column: ta = 25 c note: maximum column ta = 70 c table 10. mcimx35 power modes (continued) power mode description qvcc(arm/l2 peripheral) mvdd/pvdd osc24m_vdd osc_audo_vdd typ. max. typ. max. typ. max.
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 17 4.3.2 powering down the power-up in reverse order is recommended. however, all power supplies can be shut down at the same time. 4.4 thermal characteristics the thermal resistance characteristics for the device are given in table 11 . these values were measured under the following conditions: ? two-layer substrate ? substrate solder mask thickness: 0.025 mm ? substrate metal thicknesses: 0.016 mm ? substrate core thickness: 0.200 mm ? core via i.d: 0.168 mm, core via plating 0.016 mm. ? full array map design, but nearly all balls under die are power or ground. ? die attach: 0.033 mm non-conductiv e die attach, k = 0.3 w/m k ? mold compound: k = 0.9 w/m k 4.5 i/o pad dc electrical characteristics there are two main types of i/o: gpio and ddr. th e ddr pads can be configured in three different drive-strength modes: mobileddr, sdram, and ddr2. sdram and mobile ddr modes can be further customized within three drive strength levels: nominal, high and max. see table 12 . table 11. thermal resistance data rating condition symbol value unit junction to ambient 1 natural convection 1 junction-to-ambient thermal resistance determined per jedc jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board (1s) r eja 53 oc/w junction to ambient 1 natural convection four layer board (2s2p) r eja 30 oc/w junction to ambient 1 (@200 ft/min) single layer board (1s) r ejma 44 oc/w junction to ambient 1 (@200 ft/min) four layer board (2s2p) r ejma 27 oc/w junction to boards 2 2 junction-to-board thermal resistance determined per jedc jesd51-8. thermal test board meets jedec specification for this package. ?r ejb 19 oc/w junction to case (top) 3 3 junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. ?r ejctop 10 oc/w junction to package top 4 4 thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, this thermal characterization parameter is written as psi-jt. natural convection jt 2oc/w
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 18 table 13 shows the dc electrical characteristics for gpio, ddr2, mobile ddr, and sdram pads. the symbol nvcc refers to the power supply voltage th at feeds the i/o of the module in question. for example, if you are concerned about the sd/mmc interface then nvcc refers to nvcc_sdio. table 12. i/o drive strength modes and levels for ddr pads drive mode normal high max mobile ddr 3.6 ma 7.2 ma 10.8 ma sdram 4 ma 8 ma 12 ma ddr2 ? ? 13.4 ma
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 19 table 13. i/o pad dc electrical characteristics pad dc electrical characteristics symbol test condition min. nom. max. unit gpio high-level output voltage voh ioh=?1ma ioh=spec?ed drive nvcc-0.15 0.8*nvcc ?? v low-level output voltage vol ioh=?1ma ioh=spec?ed drive ?? 0.15 0.2*nvcc v high-level output current for slow mode ioh voh=0.8*nvcc standard drive high drive max. drive ?2.0 ?4.0 ?8.0 ?? ma high-level output current for fast mode ioh voh=0.8*nvcc standard drive high drive max. drive ?4.0 ?6.0 ?8.0 ?? ma low-level output current for slow mode iol voh=0.2*nvcc standard drive high drive max. drive 2.0 4.0 8.0 ?? ma low-level output current for fast mode iol voh=0.2*nvcc standard drive high drive max. drive 4.0 6.0 8.0 ?? ma high-level dc input voltage with 1.8v, 3.3v nvcc (for digital cells in input mode) vih ? 0.7*nvcc ? nvcc v low-level dc input voltage with 1.8v, 3.3v nvcc (for digital cells in input mode vil ? ?0.3v ? 0.2*nvcc v input hysteresis vhys nvcc=1.8 nvcc=2.5 nvcc=3.3 tbd ? tbd v schmitt trigger vt+ vt+ ? 0.5nvcc ? v schmitt trigger vt- vt- ??? 0.5nvcc v pull-up resistor (22 k pu) rpu vi=0 ? 22 ? k pull-up resistor (47 k pu) rpu vi=0 ? 47 ? k pull-up resistor (100 k pu) rpu vi=0 ? 100 ? k pull-down resistor (100 k pd) rpd vi=nvcc ? 100 ? k
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 20 ddr2 high-level output voltage voh ? nvcc?0.28 ? ? v low-level output voltage vol ? ? 0.28 v output min. source current ioh ? ?13.4 ? ? ma output min. sink current iol ? 13.4 ? ? ma dc input logic high vih(dc) ? nvcc/2+0. 125 ? nvcc+0.3 v dc input logic low vil(dc) ? ?0.3 v ? nvcc/2?0. 125 v dc input signal voltage (for differential signal) vin(dc) ? ?0.3 ? nvcc+0.3 v dc differential input voltage vid(dc) ? 0.25 ? nvcc+0.6 v termination voltage vtt ? nvcc/2?0. 04 nvcc/2 nvcc/2+0. 04 v input current (no pull-up/down) iin ? ? tbd tbd na tri-state i/o supply current icc?nvcc ? ? ? tbd na tri-state core supply current icc?vddi ? ? ? tbd na table 13. i/o pad dc electrical characteristics (continued) pad dc electrical characteristics symbol test condition min. nom. max. unit
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 21 mobile ddr high-level output voltage ? i oh = ?1ma i oh = spec?ed drive nvcc ? 0.08 0.8*nvcc ??v low-level output voltage ? i ol = 1ma i ol = spec?ed drive ?? 0.08 0.2*nvcc v high-level output current ? voh=0.8*nvccv standard drive high drive max. drive ?3.6 ?7.2 ?10.8 ??ma low-level output current ? vol=0.2*nvccv standard drive high drive max. drive 3.6 7.2 10.8 ??ma high-level dc cmos input voltage vih ? 0.7*nvcc ? nvcc+0.3 v low-level dc cmos input voltage vil ? ?0.3 ? 0.2*nvcc v differential receiver vth+ vth+ ? ? 100 mv differential receiver vth? vth? ? ?100 ? mv input current (no pull-up/ down) iin vi = 0 vi=nvcc ?? tbd na tri-state i/o supply current icc?nvcc vi = nvcc or 0 ? ? tbd na tri-state core supply current lcc?vddi vi = vdd or 0 ? ? tbd na table 13. i/o pad dc electrical characteristics (continued) pad dc electrical characteristics symbol test condition min. nom. max. unit
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 22 4.6 i/o pad ac electrical characteristics the load circuit for output pads and the output pad transition time waveform are shown in figure 2 and figure 3 . figure 2. load circuit for output pad figure 3. output pad transition time waveform sdram high-level output voltage voh ioh=spec?ed drive (ioh=?4, ?8, ?12, ?16 ma) 2.4 ? ? v low-level output voltage vol ioh=spec?ed drive (ioh=4, 8, 12, 16ma) ??0.4v high-level output current ioh standard drive high drive max. drive ?4.0 ?8.0 ?12.0 ??ma low-level output current e iol standard drive high drive max. drive 4.0 8.0 12.0 ??ma high-level dc input voltage vih ? 2.0 ? 3.6 v low-level dc input voltage vil ? ?0.3v ? 0.8 v input current (no pull-up/down) iin vi = 0 vi=nvcc ?? tbd na tri-state i/o supply current icc_ovtwdd vi = nvcc or 0 ? ? tbd na tri-state core supply current icc-vddi vi = vdd or 0 ? ? tbd na table 13. i/o pad dc electrical characteristics (continued) pad dc electrical characteristics symbol test condition min. nom. max. unit tes t poi nt from output under test cl cl includes package, probe and jig capacitance 0v nvcc 20% 80% 80% 20% pa 1 pa1 output (at pad)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 23 4.6.1 ac electrical test parameter definitions ? ac electrical characteristics in table 14 through table 19 are not applicable for the output open drain pull-down driver. ? the di/dt parameter are measured with the following methodology: ? the zero voltage source is connected between pad and load capacitance. ? the current (through this source) derivative is calculated during output transitions. table 14. ac electrical characteristics of gpio pads in slow slew rate mode [nvcc=3.0 v?3.6 v] parameter symbol test condition min. rise/fall typ. rise/fall max. rise/fall duty cycle fduty ? 40 ? 60 output pad slew rate (max. drive) tps 25 pf 50 pf 0.79/1.12 0.49/0.73 1.30/1.77 0.84/1.23 2.02/2.58 1.19/1.58 output pad slew rate (high drive) tps 25 pf 50 pf 0.48/0.72 0.27/0.42 0.76/1.10 0.41/0.62 1.17/1.56 0.63/0.86 output pad slew rate (standard drive) tps 25 pf 50 pf 0.25/0.40 0.14/0.21 0.40/0.59 0.21/0.32 0.60/0.83 0.32/0.44 output pad di/dt (max. drive) tdit 25 pf 50 pf 15 16 36 38 76 80 output pad di/dt (high drive) tdit 25 pf 50 pf 8 9 20 21 45 47 output pad di/dt (standard drive) tdit 25 pf 50 pf 4 4 10 10 22 23 table 15. ac electrical characteristics of gpio pads in slow slew rate mode [nvcc=1.65 v?1.95 v] parameter symbol test condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 ? 60 % output pad slew rate (max. drive) tps 25 pf 50 pf 0.30/0.42 0.20/0.29 0.54/0.73 0.35/0.50 0.91/1.20 0.60/0.80 v/ns output pad slew rate (high drive) tps 25 pf 50 pf 0.19/0.28 0.12/0.18 0.34/0.49 0.34/0.49 0.58/0/79 0.36/0.49 v/ns output pad slew rate (standard drive) tps 25 pf 50 pf 0.12/0.18 0.07/0.11 0.20/0.30 0.11/0.17 0.34/0.47 0.20/0.27 v/ns output pad di/dt (max. drive) tdit 25 pf 50 pf 7 7 21 22 56 58 ma/ns output pad di/dt (high drive) tdit 25 pf 50 pf 5 5 14 15 38 40 ma/ns output pad di/dt (standard drive) tdit 25 pf 50 pf 2 2 7 7 18 19 ma/ns
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 24 table 16. ac electrical characteristics of gpio pads in fast slew rate mode for [nvcc=3.0 v?3.6 v] parameter symbol test condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 ? 60 % output pad slew rate (max. drive) tps 25 pf 50 pf 0.96/1.40 0.54/0.83 1.54/2.10 0.85/1.24 2.30/3.00 1.26/1.70 v/ns output pad slew rate (high drive) tps 25 pf 50 pf 0.76/1.10 0.41/0.64 1.19/1.71 0.63/0.95 1.78/2.39 0.95/1.30 v/ns output pad slew rate (standard drive) tps 25 pf 50 pf 0.52/0.78 0.28/0.44 0.80/1.19 0.43/0.64 1.20/1.60 0.63/0.87 v/ns output pad di/dt (max. drive) tdit 25 pf 50 pf 46 49 108 113 250 262 ma/ns output pad di/dt (high drive) tdit 25 pf 50 pf 35 37 82 86 197 207 ma/ns output pad di/dt (standard drive) tdit 25 pf 50 pf 22 23 52 55 116 121 ma/ns table 17. ac electrical characteristics, gpio pads in fast slew rate mode [nvcc=1.65 v?1.95 v] parameter symbol test condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 ? 60 % output pad slew rate (max. drive) tps 25 pf 50 pf 0.40/0.57 0.25/0.36 0.72/0.97 0.43/0.61 1.2/1.5 0.72/0.95 v/ns output pad slew rate (high drive) tps 25 pf 50 pf 0.38/0.48 0.20/0.30 0.59/0.81 0.34/0.50 0.98/1.27 0.56/0.72 v/ns output pad slew rate (standard drive) tps 25 pf 50 pf 0.23/0.32 0.13/0.20 0.40/0.55 0.23/0.34 0.66/0.87 0.38/0.52 v/ns output pad di/dt (max. drive) tdit 25 pf 50 pf 7 7 43 46 112 118 ma/ns output pad di/dt (high drive) tdit 25 pf 50 pf 11 12 31 33 81 85 ma/ns output pad di/dt (standard drive) tdit 25 pf 50 pf 9 10 27 28 71 74 ma/ns table 18. ac electrical characteristics of gpio pads in slow slew rate mode [nvcc=2.25 v?2.75 v] parameter symbol test condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 ? 60 % output pad slew rate (max. drive) tps 25 pf 40 pf 50 pf 0.63/0.85 0.52/0.67 0.41/0.59 1.10/1.40 0.90/1.10 0.73/0.99 1.86/2.20 1.53/1.73 1.20/1.50 v/ns
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 25 output pad slew rate (high drive) tps 25 pf 40 pf 50 pf 0.40/0.58 0.33/0.43 0.25/0.37 0.71/0.98 0.56/0.70 0.43/0.60 1.16/1.40 0.93/1.07 0.68/0.90 v/ns output pad slew rate (standard drive) tps 25 pf 40 pf 50 pf 0.24/0.36 0.19/0.25 0.13/0.21 0.41/0.59 0.32/0.35 0.23/0.33 0.66/0.87 0.51/0.59 0.36/0.48 v/ns output pad di/dt (max. drive) tdit 25 pf 50 pf 22 23 62 65 148 151 ma/ns output pad di/dt (high drive) tdit 25 pf 50 pf 15 16 42 44 102 107 ma/ns output pad di/dt (standard drive) tdit 25 pf 50 pf 7 8 21 22 52 54 ma/ns table 19. ac electrical characteristics of gpio pads in fast slew rate mode [nvcc=2.25 v?2.75 v] parameter symbol test condition min. rise/fall typ. max. rise/fall units notes duty cycle fduty ? 40 ? 60 % ? output pad slew rate (max. drive) tps 25 pf 40 pf 50 pf 0.84/1.10 0.68/0.83 0.58/0.72 1.45/1.80 1.14/1.34 0.86/1.10 2.40/2.80 1.88/2.06 1.40/1.70 v/ns 2 output pad slew rate (high drive) tps 25 pf 40 pf 50 pf 0.69/0.96 0.55/0.69 0.40/0.59 1.18/1.50 0.92/1.10 0.67/0.95 1.90/2.30 1.49/1.67 1.10/1.30 v/ns output pad slew rate (standard drive) tps 25 pf 40 pf 50 pf 0.24/0.36 0.37/0.47 0.13/0.21 0.80/1.00 0.62/0.76 0.45/0.65 1.30/1.60 1.00/1.14 0.70/0.95 v/ns output pad di/dt (max. drive) tdit 25 pf 50 pf 46 49 124 131 310 324 ma/ns 3 output pad di/dt (high drive) tdit 25 pf 50 pf 33 35 89 94 290 304 ma/ns output pad di/dt (standard drive) tdit 25 pf 50 pf 28 29 75 79 188 198 ma/ns table 18. ac electrical characteristics of gpio pads in slow slew rate mode [nvcc=2.25 v?2.75 v] parameter symbol test condition min. rise/fall typ. max. rise/fall units
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 26 4.6.2 ac electrical characteristics for ddr pads (ddr2, mobile ddr, and sdram modes) table 20. ac electrical characteristics of ddr type io pads in ddr2 mode parameter symbol test condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 50 60 % clock frequency f ? ? 133 ? mhz output pad slew rate tps 25 pf 50 pf 0.86/0.98 0.46/054 1.35/1.5 0.72/0.81 2.15/2.19 1.12/1.16 v/ns output pad di/dt tdit 25 pf 50 pf 65 70 157 167 373 396 ma/ns table 21. ac requirements of ddr2 pads parameter 1 1 the jedec sstl_18 specification (jesd8?15a) for a sstl interface for class ii operation supersedes any specification in this document. symbol min. max. units ac input logic high vih(ac) nvcc/2+0.25 nvcc+0.3 v ac input logic low vil(ac) ?0.3 nvcc/2?0.25 v ac differential cross point voltage for output 2 2 the typical value of vox(ac) is expected to be about 0.5*nvcc and vox(ac) is expected to track variation in nvcc. vox(ac) indicates the voltage at which the differential output signal must cross. cload=25 pf. vox(ac) nvcc/2?0.125 nvcc/2+0.125 v table 22. ac electrical characteristics of ddr type io pads in mobileddr mode, fast slew rate parameter symbol test condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 50 60 % clock frequency f ? ? 133 ? mhz output pad slew rate (max. drive) tps 25pf 50pf 0.80/0.92 0.43/0.50 1.35/1.50 0.72/0.81 2.23/2.27 1.66/1.68 v/ns output pad slew rate (high drive) tps 25pf 50pf 0.37/0.43 0.19/0.23 0.62/0.70 0.33/0.37 1.03/1.05 0.75/0.77 v/ns output pad slew rate (standard drive) tps 25pf 50pf 0.18/0.22 0.10/0.12 0.31/0.35 0.16/0.18 0.51/0.53 0.38/0.39 v/ns output pad di/dt (max. drive) tdit 25pf 50pf 64 69 171 183 407 432 ma/ns output pad di/dt (high drive) tdit 25pf 50pf 37 39 100 106 232 246 ma/ns output pad di/dt (standard drive) tdit 25pf 50pf 18 20 50 52 116 123 ma/ns
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 27 table 23. ac electrical characteristics of ddr type io pads in mobileddr mode, slow slew rate parameter symbol test condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 50 60 % clock frequency f ? ? 133 ? mhz output pad slew rate (max. drive) tps 25pf 50pf 0.37/0.45 0.30/0.36 0.64/0.79 0.52/0.61 1.14/1.36 0.90/1.02 v/ns output pad slew rate (high drive) tps 25pf 50pf 0.30/0.37 0.21/0.25 0.51/0.63 0.36/0.42 091/1.06 0.63/0.67 v/ns output pad slew rate (standard drive) tps 25pf 50pf 0.22/0.26 0.13/0.16 0.37/0.44 0.23/0.26 0.65/0.72 0.39/0.40 v/ns output pad di/dt (max. drive) tdit 25pf 50pf 65 70 171 183 426 450 ma/ns output pad di/dt (high drive) tdit 25pf 50pf 31 33 82 87 233 245 ma/ns output pad di/dt (standard drive) tdit 25pf 50pf 16 17 43 46 115 120 ma/ns table 24. ac electrical characteristics of ddr type io pads in sdram mode, fast slew rate parameter symbol test condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 50 60 % clock frequency f ? ? 125 ? mhz output pad slew rate (max. drive) tps 25pf 50pf 1.11/1.20 0.97/0.65 1.74/1.75 0.92/0.94 2.42/2.46 1.39/1.30 v/ns output pad slew rate (high drive) tps 25pf 50pf 0.76/0.80 0.40/0.43 1.16/1.19 0.61/0.63 1.76/1.66 0.93/0.87 v/ns output pad slew rate (standard drive) tps 25pf 50pf 0.38/0.41 0.20/0.22 0.59/0.60 0.31/0.32 0.89/0.82 0.47/0.43 v/ns output pad di/dt (max. drive) tdit 25 pf 50 pf 89 94 198 209 398 421 ma/ns output pad di/dt (high drive) tdit 25 pf 50 pf 59 62 132 139 265 279 ma/ns output pad di/dt (standard drive) tdit 25 pf 50 pf 29 31 65 69 132 139 ma/ns table 25. ac electrical characteristics of ddr type io pads in mobileddr mode. slow slew rate parameter symbol test condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 50 60 % clock frequency f ? ? 125 ? mhz
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 28 4.7 module-level ac electrical specifications this section contains the ac electrical informati on (including timing specifications) for different modules of the mcimx35. the modules are listed in alphabetical order. 4.7.1 audmux electrical specifications the audmux provides a programmable interconnect logi c for voice, audio and data routing between internal serial interfaces (ssi) and external serial interfaces (audio and voice codecs). the ac timing of audmux external pins is hence governed by the ss i module. see the electrical specification for ssi. 4.7.2 cspi ac electrical specifications the mcimx35 provides two cspi modules. cspi ports are multiplexed in the mcimx35 with other pads. see the iomux chapter of the reference manual for more details. figure 4 and figure 5 depict the master mode and slave mode timings of cspi, and table 26 lists the timing parameters. output pad slew rate (max. drive) tps 25pf 50pf 1.11/1.20 0.60/0.65 1.74/1.75 0.93/0.95 2.63/2.48 1.39/1.29 v/ns output pad slew rate (high drive) tps 25pf 50pf 0.75/0.81 0.40/0.43 1.16/1.18 0.62/0.64 1.76/1.65 094/0.87 v/ns output pad slew rate (standard drive) tps 25pf 50pf 0.38/0.41 0.20/0.22 0.59/0.61 0.31/0.32 0.89/0.83 0.47/0.43 v/ns output pad di/dt (max. drive) tdit 25 pf 50 pf 89 95 202 213 435 456 ma/ns output pad di/dt (high drive) tdit 25 pf 50 pf 60 63 135 142 288 302 ma/ns output pad di/dt (standard drive) tdit 25 pf 50 pf 29 31 67 70 144 150 ma/ns table 25. ac electrical characteristics of ddr type io pads in mobileddr mode. slow slew rate parameter symbol test condition min. rise/fall typ. max. rise/fall units
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 29 figure 4. cspi master mode timing diagram figure 5. cspi slave mode timing diagram table 26. cspi interface timing parameters id parameter symbol min. max. units cs1 sclk cycle time t clk 60 ? ns cs2 sclk high or low time t sw 30 ? ns cs3 sclk rise or fall t rise/fall ?7.6ns cs4 ss n [3:0] pulse width t cslh 30 ? ns cs5 ss n [3:0] lead time (cs setup time) t scs 30 ? ns cs6 ss n [3:0] lag time (cs hold time) t hcs 30 ? ns cs7 mosi setup time t smosi 5?ns cs8 mosi hold time t hmosi 5?ns cs9 miso setup time t smiso 5?ns cs10 miso hold time t hmiso 5?ns cs11 spi_rdy setup time t sdry 5?ns cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 cs10 sclk ss n [3:0] mosi miso spi_rdy cs11 cs3 cs3 cs7 cs8 cs2 cs2 cs4 cs6 cs9 cs10 sclk ss n [3:0] miso mosi cs1 cs3 cs3 cs5
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 30 4.7.3 dpll electrical specifications there are three plls inside the mcimx35, all based on the same pll design. the reference clock for these plls is normally generated from an external 24- mhz crystal connected to an internal oscillator via extal24m and xtal24 pads. it is also possible to connect an external 24-mhz clock directly to extal24m, bypassing the internal oscillator. dpll specifications are listed in table 27 . 4.7.4 embedded trace macrocell (etm) electrical specifications etm is an arm protocol. the timing specifications in this section are given as a guide for a test point access (tpa) that supports traceclk frequencies up to 133 mhz. figure 6 depicts the traceclk timings of etm, and table 28 lists the timing parameters. figure 6. etm traceclk timing diagram table 27. dpll specifications parameter min. typ. max. unit comments reference clock frequency 10 24 100 mhz max. allowed reference clock phase noise ??0.03 0.01 0.15 2 tdck 1 1 there are two pll are used in the mcimx35, mpll and ppll. both are based on same dpll design. fmodulation <50 khz 50 khz 300 khz frequency lock time (fol mode or non-integer mf) ?? 80 s ? phase lock time ? ? 100 s? max. allowed pl voltage ripple ? ? 150 100 150 mv fmodulation < 50 khz 50 khz < fmodulation 300 hz fmodulation > 300 khz table 28. etm traceclk timing parameters id parameter min. max. unit t cyc clock period frequency dependent ? ns t wl low pulse width 2 ? ns t wh high pulse width 2 ? ns
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 31 figure 7 depicts the setup and hold requirements of the tr ace data pins with respect to traceclk, and table 29 lists the timing parameters. figure 7. trace data timing diagram 4.7.4.1 half-rate clocking mode when half-rate clocking is used, the trace data si gnals are sampled by the tpa on both the rising and falling edges of traceclk, where traceclk is half the frequency of the clock shown in figure 7 . the same t s and t h parameters from table 29 still apply with respect to the falling edge of the traceclk signal. 4.7.5 emi electrical specifications this section provides electrical parametrics and timing for the emi module. 4.7.5.1 nand flash controller interface (nfc) the mcimx35 nfc supports normal timing mode, using two flash clock cycles for one access of re and we . ac timings are provided as multiplications of the clock cycle and fixed delay. figure 8 , figure 9 , figure 10 , and figure 11 depict the relative timing requirements among different signals of the nfc at module level, for normal mode, and table 30 lists the timing parameters. t r clock and data rise time ? 3 ns t f clock and data fall time ? 3 ns table 29. etm trace data timing parameters id parameter min. max. unit t s data setup 2 ? ns t h data hold 1 ? ns table 28. etm traceclk timing parameters (continued) id parameter min. max. unit
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 32 figure 8. command latch cycle timing diagram figure 9. address latch cycle timing diagram nfcle nfce nfwe nfale nfio[7:0] command nf9 nf8 nf1 nf2 nf5 nf3 nf4 nf6 nf7 nfcle nfce nfwe nfale nfio[7:0] address nf9 nf8 nf1 nf5 nf3 nf4 nf6 nf11 nf10 nf7
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 33 figure 10. write data latch cycle timing diagram figure 11. read data latch cycle timing diagram table 30. nfc timing parameters 1 id parameter symbol timing t = nfc clock cycle 2 example timing for nfc clock 33 mhz t = 30 ns unit min. max. min. max. nf1 nfcle setup time tcls t?1.0 ns ? 29 ? ns nf2 nfcle hold time tclh t?2.0 ns ? 28 ? ns nf3 nfce setup time tcs t?1.0 ns ? 29 ? ns nf4 nfce hold time tch t?2.0 ns ? 28 ? ns nfcle nfce nfwe nfale nfio[15:0] data to nf nf9 nf8 nf1 nf5 nf3 nf6 nf11 nf10 nf7 nfcle nfce nfre nfrb nfio[15:0] data from nf nf13 nf15 nf14 nf17 nf12 nf16
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 34 note high is defined as 80% of signal value and low is defined as 20% of signal value. timing for hclk is 133 mhz and internal nfc clock (flash clock) is approximately 33 mhz (30 ns). all timings are listed according to this nfc clock frequency (multiples of nfc clock phases), except nf16 and nf17, which are not nfc clock related. 4.7.5.2 wireless external interface module (weim) the following diagrams and tables specify the timi ngs related to the weim module. all weim output control signals may be asserted and deasserted by in ternal clock related to bclk rising edge or falling edge according to corresponding assertion/negation contro l fields. the address always begins relative to the bclk falling edge, but may be ended both on rising and falling edge in the muxed mode according to control register configuration. output data begins relative to bclk rising edge except in muxed mode, where both rising and falling edge may be used according to the control register configuration. input data, ecb_b and dtack_b all captured according to bclk rising edge time. nf5 nf_wp pulse width twp t?1.5 ns 28.5 ns nf6 nfale setup time tals t ? 30 ? ns nf7 nfale hold time talh t?3.0 ns ? 27 ? ns nf8 data setup time tds t ? 30 ? ns nf9 data hold time tdh t?5.0 ns ? 25 ? ns nf10 write cycle time twc 2t 60 ns nf11 nfwe hold time twh t?2.5 ns 27.5 ns nf12 ready to nfre low trr 6t ? 180 ? ns nf13 nfre pulse width trp 1.5t ? 45 ? ns nf14 read cycle time trc 2t ? 60 ? ns nf15 nfre high hold time treh 0.5t?2.5 ns 12.5 ? ns nf16 data setup on read tdsr n/a 10 ? ns nf17 data hold on read tdhr n/a 0 ? ns 1 the flash clock maximum frequency is 50 mhz. 2 subject to dpll jitter specification listed in table 27, "dpll specifications," on page 30 . table 30. nfc timing parameters 1 (continued) id parameter symbol timing t = nfc clock cycle 2 example timing for nfc clock 33 mhz t = 30 ns unit min. max. min. max.
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 35 note the dtack_b signal can be muxed to different pins on the chip-level. in those cases, see the system configuration section for the corresponding pin name. the address and data pin names are determined by the weim mode. , figure 12. weim outputs timing diagram figure 13. weim inputs timing diagram we4 address csx_b rw_b oe_b bclk eby_b lba_b output data ... we5 we6 we7 we8 we9 we10 we11 we12 we13 we14 we15 we16 we17 we3 we2 we1 input data ecb_b dtack_b bclk we20, we21 we18, we19 we24, we25 we22, we23 we27 we26
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 36 table 31. weim bus timing parameters 1 id parameter 1.8 v unit min. max. we1 bclk cycle time 2 7.5 ns we2 bclk low level width 2 3.0 ns we3 bclk high level width 2 3.0 ns we4 clock fall to address valid ?1.0 2.0 ns we5 clock rise/fall to address invalid ?1.0 2.0 ns we6 clock rise/fall to csx_b] valid ?1.0 2.0 ns we7 clock rise/fall to csx_b] invalid ?1.0 2.0 ns we8 clock rise/fall to rw_b valid ?1.0 2.0 ns we9 clock rise/fall to rw_b invalid ?1.0 2.0 ns we10 clock rise/fall to oe_b valid ?1.0 2.0 ns we11 clock rise/fall to oe_b invalid ?1.0 2.0 ns we12 clock rise/fall to eby_b valid ?1.0 1.50 ns we13 clock rise/fall to eby_b invalid ?1.0 1.50 ns we14 clock rise/fall to lba_b valid ?1.0 2.0 ns we15 clock rise/fall to lba_b invalid ?1.0 2.0 ns we16 clock rise/fall to output data valid ?1.0 1.50 1 ns we17 clock rise to output data invalid ?1.0 1.50 1 ns we18 input data valid to clock rise, fce=1 1.2 ns we19 input data valid to clock rise, fce=0 7.2 ns we20 clock rise to input data invalid, fce=1 0.2 ns we21 clock/k rise to input data invalid, fce=0 2.4 ns we22 ecb_b setup time, fce=1 1.2 ns we23 ecb_b setup time, fce=0 7.2 ns we24 ecb_b hold time, fce=1 0.2 ns we25 ecb_b hold time, fce=0 2.4 ns we26 dtack_b setup time 5.4 ns we27 dtack_b hold time ?3.2 ns
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 37 the following diagrams give a few examples of basic weim accesses to external memory devices with the timing parameters mentioned previously for specific control parameters settings. figure 14. asynchronous memory read access, wsc=1. 1 in case of dol=1 and bclk 66mhz, max time for we16 and we17 is 2.5ns. high is defined as 80% of signal value and low is defined as 20% of signal value. bclk parameters are being measured from the 50% point. i.e., high is defined as 50% of signal value and low is defined as 50% as signal value. note: test conditions are: pad voltage 1.7v?1.95v, capacitance 25 pf for pads. note: recommended drive strength for all controls, address and bclk is max drive. last valid address address v1 d(v1) bclk addr data rw_b lba_b oe_b eby_b csx_b next address we4 we5 we6 we7 we10 we11 we13 we12 we14 we15 we18 we20
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 38 figure 15. asynchronous memory, write access, wsc=1, ebwa=1, ebwn=1, lbn=1. figure 16. synchronous 16-bit memory, two non-sequential 32-bit read accesses, wsc=2, sync=1, dol=0 last valid address address v1 d(v1) bclk addr data rw_b lba_b oe_b eby_b csx_b next address we4 we5 we6 we7 we8 we9 we12 we13 we14 we15 we16 we17 last valid addr address v1 address v2 d(v1) d(v1+1) d(v2) d(v2+1) bclk addr ecb_b data halfword halfword csx_b rw_b lba_b oe_b eby_b halfword halfword we4 we5 we7 we10 we11 we12 we13 we14 we15 we18 we20 we22 we24 we6
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 39 figure 17. synchronous memory, burst write, bcs=1, wsc=4, sync=1, dol=0, psr=1 figure 18. muxed a/d mode, asynchronous wr ite access, wsc=7, lba=1, lbn=1, lah=1 last valid addr bclk addr data csx_b rw_b lba_b oe_b eby_b ecb_b address v1 d(v1) d(v2) d(v4) d(v3) we12 we4 we5 we6 we7 we8 we9 we13 we14 we16 we16 we17 we17 we22 we24 last write bclk addr/ rw_b lba_b oe_b eby_b csx_b address v1 write data valid addr m_data we4 we5 we6 we7 we9 we8 we10 we11 we14 we15 we16 we17
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 40 figure 19. muxed a/d mode, asynchronous read access, wsc=7, lba=1, lbn=1, lah=1, oea=7 figure 20 , figure 21 , and table 32 help to determine timing parameters relative chip select state for asynchronous weim accesses with correspondent weim bit fields and the timing parameters above mentioned. figure 20. asynchronous memory read access last bclk addr/ rw_b lba_b oe_b eby_b csx_b address v1 read data valid addr m_data we5 we6 we7 we14 we15 we10 we11 we12 we13 we18 we20 we4 last valid address address v1 d(v1) addr data rw_b lba_b oe_b eby_b csx_b next address we39 we35 we37 we32 we36 we38 we44 we43 we40 we31
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 41 figure 21. asynchronous memory write access table 32. weim asynchronous timing parameters table relative chip select ref no. parameter determination by synchronous measured parameters 1 1.8 v unit min max we31 csx_b valid to address valid we4 ? we6 ? csa hhc 2 1.6 ? csa hhc ns we32 address invalid to csx_b invalid we7 ? we5 ? csn hhc ?2.1 ? csn hhc ns we33 csx_b valid to rw_b valid we8 ? we6 + (rwa ? csa) hhc 1.9 + (rwa ? csa) hhc ns we34 rw_b invalid to csx_b invalid we7 ? we9 + (rwn ? csn) hhc ?1.6 + (rwn ? csn) hhc ns we35 csx_b valid to oe_b valid we10 ? we6 + (oea ? csa) hhc 1.8 + (oea ? csa) hhc ns we36 oe_b invalid to csx_b invalid we7 ? we11 + (oen ? csn) hhc ?1.3 + (oen ? csn) hhc ns we37 csx_b valid to eby_b valid (read access) we12 ? we6 + (ebra ? csa) hhc 1.7 + (ebra ? csa) hhc ns we38 eby_b invalid to csx_b invalid (read access) we7 ? we13 + (ebrn ? csn) hhc ?1.8 + (ebrn ? csn) hhc ns we39 csx_b valid to lba_b valid we14 ? we6 + (lba ? csa) hhc 2.1 + (lba ? csa) hhc ns we40 lba_b invalid to csx_b invalid we7 ? we15 + (lbn ? csn) hhc ?1.5 + (lbn ? csn) hhc ns we41 csx_b valid to output data valid we16 ? we6 + (1 ? csa) hhc 2.3 + (1 ? csa) hhc ns we42 csx_b invalid to output data invalid we17 ? we7 + (1 ? csn) hhc ?1.5 + (1 ? csn) hhc ns last valid address address v1 d(v1) addr data rw_b lba_b oe_b eby_b csx_b next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 42 1 parameters we4... we21 value see in the ta b l e 3 1 . 2 here hhc is a half hclk period. it is 3.75 ns in default case then hclk is 133 mhz. 3 here maxn = (oen[3:1] ? csn[3:1])*2 in case oen[3:1] > csn[3:1], in other cases maxn = 0. figure 22 , figure 23 , and table 33 help to determine timing parameters relative address bus valid state for asynchronous weim accesses with correspondent weim bit fields and the timing parameters above mentioned. figure 22. asynchronous memory read access we43 input data valid to csx_b invalid we19 + we6 + (csn[0] ? 1 + maxn) hhc 3 4.9 + (csn[0] ? 1 + maxn) hhc ns we44 csx_b invalid to input data invalid we21+ we7 + (1 ? csn[0] + maxn) hhc 0.7 + (1 ? csn[0] + maxn) hhc ns we45 csx_b valid to eby_b valid (write access) we12 ? we6 + (ebwa ? csa) hhc 1.7 + (ebwa ? csa) hhc ns we46 eby_b invalid to csx_b invalid (write access) we7 ? we13 + (ebwn ? csn) hhc ?1.8 + (ebwa ? csa) hhc ns table 32. weim asynchronous timing parameters table relative chip select (continued) ref no. parameter determination by synchronous measured parameters 1 1.8 v unit min max last valid address address v1 d(v1) addr data rw_b lba_b oe_b eby_b csx_b next address we50 we58 we54 we56 we51 we55 we57 we63 we62 we59
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 43 figure 23. asynchronous memory write access table 33. weim asynchronous timing parameters table relative address bus valid ref no. parameter determination by synchronous measured parameters 1 1.8 v unit min max we50 address valid to csx_b valid we6 ? we4 + csa hhc 2 1.6+ csa hhc ns we51 csx_b invalid to address invalid we5 ? we7 + csn hhc ? 1.6 + csn hhc ns we52 address valid to rw_b valid we8 ? we4 + rwa hhc 2.2 + rwa hhc ns we53 rw_b invalid to address invalid we5 ? we9 + rwn hhc ? 1.4 + rwn hhc ns we54 address valid to oe_b valid we10 ? we4 + oea hhc 2.1 + oea hhc ns we55 oe_b invalid to address invalid we5 ? we11 + oen hhc ? 1.1 + oen hhc ns we56 address valid to eby_b valid (read access) we12 ? we4 + ebra hhc 2.0 + ebra hhc ns we57 eby_b invalid to address invalid (read access) we5 ? we13 + ebrn hhc ? 1.6 + ebrn hhc ns we58 address valid to lba_b valid we14 ? we4 + lba hhc 2.4 + lba hhc ns we59 lba_b invalid to address invalid we5 ? we15 + lbn hhc ? 1.3 + lbn hhc ns we60 address valid to output data valid we16 ? we4 + hhc 2.6 + hhc ns we61 address invalid to output data invalid we17 ? we5 + hhc ? 1.3 + hhc ns we62 input data valid to address invalid we19 + we4 + (1 + maxn) hhc 3 4.6 + (1 + maxn) hhc ns last valid address address v1 d(v1) addr data rw_b lba_b oe_b eby_b csx_b next address we50 we58 we52 we64 we51 we59 we53 we65 we61 we60
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 44 1 parameters we4... we21 value see in the

table 31.. 2 here hhc is a half hclk period. it is 3.75 ns in default case then hclk is 133 mhz. 3 here maxn is maximum from (oen & 4?b1110) or (csn & 4?b1110). 4.7.5.3 esdctl electrical specifications 4.7.5.3.1 sdram memory controller the following diagrams and tables specify the timi ngs related to the sdramc module which interfaces sdram. we63 address invalid to input data invalid we23 ? we5 + (maxn ? 1) hhc ? 0.4 + (maxn ? 1) hhc ns we64 address valid to eby_b valid (write access) we12 ? we4 + ebwa hhc 2.0 + ebwa hhc ns we65 eby_b invalid to address invalid (write access) we5 ? we13 + ebwn hhc ? 1.6 + ebwn hhc ns table 33. weim asynchronous timing parameters table relative address bus valid (continued) ref no. parameter determination by synchronous measured parameters 1 1.8 v unit min max
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 45 figure 24. sdram read cycle timing diagram table 34. sdram timing parameter table id parameter symbol min max unit sd1 sdram clock high-level width tch 0.45 0.55 tck sd2 sdram clock low-level width tcl 0.45 0.55 tck sd3 sdram clock cycle time tck 7.5 ? ns sd4 cs, ras, cas, we, dqm, cke setup time tcms 2.3 ? ns sd5 cs, ras, cas, we, dqm, cke hold time tcmh 1.3 ? ns sd6 address setup time tas 2.4 ? ns sd7 address output hold time tah 1.4 ? ns sdclk we addr dq dqm row/ba col/ba data cs cas ras note: cke is high during the read/write cycle. sd4 sd1 sd3 sd2 sd4 sd4 sd4 sd4 sd5 sd5 sd5 sd5 sd5 sd6 sd7 sd8 sd9 sdclk
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 46 figure 25. sdram write cycle timing diagram sd8 sdram access time tac 1.8 6.5 ns sd9 data out hold time toh 1.4 ? ns table 35. sdram write timing parameter table id parameter symbol min. max. unit sd1 sdram clock high-level width tch 0.45 0.55 tck sd2 sdram clock low-level width tcl 0.45 0.55 tck sd3 sdram clock cycle time tck 7.5 ? ns table 34. sdram timing parameter table (continued) id parameter symbol min max unit cs cas we ras addr dq dqm ba row / ba col/ba data sd4 sd4 sd4 sd4 sd5 sd5 sd5 sd5 sd7 sd6 sd13 sd14 sdclk sd1 sd3 sd2 sdclk
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 47 4.7.5.3.2 mobile ddr sdram specific parameters the following diagrams and tables specify the timi ngs related to the sdramc module which interfaces with the mobile ddr sdram. figure 26. mobile ddr sdram timing diagram sd4 cs, ras, cas, we, dqm, cke setup time tcms 2.3 ? ns sd5 cs, ras, cas, we, dqm, cke hold time tcmh 1.3 ? ns sd6 address setup time tas 2.4 ? ns sd7 address hold time tah 1.4 ? ns sd13 data setup time tds 2.4 ? ns sd14 data hold time tdh 1.4 ? ns table 35. sdram write timing parameter table (continued) id parameter symbol min. max. unit sdclk we addr row/ba col/ba cs cas ras ddr1 ddr3 ddr2 ddr4 ddr4 ddr4 ddr5 ddr5 ddr5 ddr5 ddr6 ddr7 sdclk cke ddr8 ddr4
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 48 figure 27. mobile ddr sdram write cycle timing diagram table 36. mobile ddr sdram timing parameter table id parameter symbol unit min max ddr1 sdram clock high-level width tch 0.45 0.55 tck ddr2 sdram clock low-level width tcl 0.45 0.55 tck ddr3 sdram clock cycle time tck 7.5 ? ns ddr4 cs, ras, cas, we, dqm setup time tcms 2.3 ? ns ddr5 cs, ras, cas, we, dqm hold time tcmh 1.3 ? ns ddr6 address output setup time tas 1.4 ? ns ddr7 address output hold time tah 1.4 ? ns ddr8 cke setup time tcks 2.5 ? ns table 37. mobile ddr sdram write cycle parameter table id parameter symbol min max unit dd17 dq & dqm setup time to dqs tds 1.2 ? ns dd18 dq & dqm hold time to dqs tdh 1.2 ? ns dd19 write cycle dqs falling edge to sdclk output delay time. tdss 0.25 ? tck dd20 write cycle dqs falling edge to sdclk output hold time. tdsh 0.25 ? tck sdclk sdclk_b dqs (output) dq (output) dqm (output) data data data data data data data data dm dm dm dm dm dm dm dm dd17 dd17 dd17 dd17 dd18 dd18 dd18 dd18 dd19 dd20
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 49 figure 28. mobile ddr sdram dq vs. dqs and sdclk read cycle timing diagram 4.7.5.3.3 ddr2 sdram specific parameters the following diagrams and tables specify the timi ngs related to the sdramc module which interfaces ddr2 sdram. table 38. mobile ddr sdram read cycle parameter table id parameter symbol min max unit dd21 dqs - dq skew (defines the data valid window in read cycles related to dqs). tdqsq ? 0.85 ns dd22 dqs dq hold time from dqs tqh 2.5 ? ns dd23 dqs output access time from sdclk posedge tdqsck 2 6.5 ns sdclk sdclk_b dqs (input) dq (input) data data data data data data data data dd23 dd21 dd22
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 50 figure 29. ddr2 sdram basic timing parameters table 39. ddr2 sdram timing parameter table id parameter symbol min max unit ddr1 sdram clock high-level width t ch 0.45 0.55 t ck ddr2 sdram clock low-level width t cl 0.45 0.55 t ck ddr3 sdram clock cycle time t ck 7.5 8 ns ddr4 cs, ras, cas, cke, we setup time t is 0.35 ? ns ddr5 cs, ras, cas, cke, we hold time t ih 0.475 ? ns ddr6 address output setup time t is 0.35 ? ns ddr7 address output hold time t ih 0.475 ? ns sdclk we addr row/ba col/ba cs cas ras ddr1 ddr3 ddr2 ddr4 ddr4 ddr4 ddr5 ddr5 ddr5 ddr5 ddr6 ddr7 sdclk cke ddr4 ddr4
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 51 figure 30. ddr2 sdram write cycle timing diagram figure 31. ddr2 sdram dq vs. dqs and sdclk read cycle timing diagram table 40. ddr2 sdram write cycle parameter table id parameter symbol min max unit ddr17 dq & dqm setup time to dqs (single-ended strobe) t ds(base) 0.025 ? ns ddr18 dq & dqm hold time to dqs (single-ended strobe) t dh(base) 0.025 ? ns ddr19 write cycle dqs falling edge to sdclk output setup time. t dss 0.2 ? tck ddr20 write cycle dqs falling edge to sdclk output hold time. t dsh 0.2 ? tck ddr21 dqs latching rising transitions to associated clock edges t dqss -0.25 0.25 tck ddr22 dqs high level width t dqsh 0.35 ? tck ddr23 dqs low level width t dqsl 0.35 ? tck sdclk sdclk_b dqs (output) dq (output) dqm (output) data data data data data data data data dm dm dm dm dm dm dm dm ddr17 ddr17 ddr17 ddr17 ddr18 ddr18 ddr18 ddr18 ddr19 ddr20 ddr21 ddr23 ddr22 sdclk sdclk_b dqs (input) dq (input) data data data data data data data data ddr26 ddr24 ddr25
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 52 table 41. ddr2 sdram read cycle parameter table id parameter symbol min max unit ddr24 dqs - dq skew (defines the data valid window in read cycles related to dqs). t dqsq ?0.35ns ddr25 dqs dq in hold time from dqs 1 t qh 2.925 ? ns ddr26 dqs output access time from sdclk posedge t dqsck -0.5 0.5 ns
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 53 4.7.6 enhanced serial audio interface (esai) timing specifications the esai consists of independent transmitter and receiver sections, each section with its own clock generator. table 42 shows the interface timing values. the number field in the table refers to timing signals found in figure 32 and figure 33 . table 42. enhanced serial audio interface timing no. characteristics 1,2 symbol expression 2 min. max. condition 3 unit 62 clock cycle 4 t ssicc 4 t c 4 t c 30.0 30.0 ? ? i ck i ck ns 63 clock high period ? for internal clock ?2 t c ? 9.0 6 ? ? ns ? for external clock 2 t c 15 ? 64 clock low period ? for internal clock ?2 t c ? 9.0 6 ? ? ns ? for external clock 2 t c 15 ? 65 sckr rising edge to fsr out (bl) high ? ? ? ? 17.0 7.0 x ck i ck a ns 66 sckr rising edge to fsr out (bl) low ? ? ? ? 17.0 7.0 x ck i ck a ns 67 sckr rising edge to fsr out (wr) high 5 ??? ? 19.0 9.0 x ck i ck a ns 68 sckr rising edge to fsr out (wr) low 5 ??? ? 19.0 9.0 x ck i ck a ns 69 sckr rising edge to fsr out (wl) high ? ? ? ? 16.0 6.0 x ck i ck a ns 70 sckr rising edge to fsr out (wl) low ? ? ? ? 17.0 7.0 x ck i ck a ns 71 data in setup time before sckr (sck in synchronous mode) falling edge ? ? 12.0 19.0 ? ? x ck i ck ns 72 data in hold time after sckr falling edge ? ? 3.5 9.0 ? ? x ck i ck ns 73 fsr input (bl, wr) high before sckr falling edge 5 ??2.0 12.0 ? ? x ck i ck a ns 74 fsr input (wl) high before sckr falling edge ? ? 2.0 12.0 ? ? x ck i ck a ns 75 fsr input hold time after sckr falling edge ? ? 2.5 8.5 ? ? x ck i ck a ns 78 sckt rising edge to fst out (bl) high ? ? ? ? 18.0 8.0 x ck i ck ns 79 sckt rising edge to fst out (bl) low ? ? ? ? 20.0 10.0 x ck i ck ns
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 54 80 sckt rising edge to fst out (wr) high 5 ??? ? 20.0 10.0 x ck i ck ns 81 sckt rising edge to fst out (wr) low 5 ??? ? 22.0 12.0 x ck i ck ns 82 sckt rising edge to fst out (wl) high ? ? ? ? 19.0 9.0 x ck i ck ns 83 sckt rising edge to fst out (wl) low ? ? ? ? 20.0 10.0 x ck i ck ns 84 sckt rising edge to data out enable from high impedance ??? ? 22.0 17.0 x ck i ck ns 86 sckt rising edge to data out valid ? ? ? ? 18.0 13.0 x ck i ck ns 87 sckt rising edge to data out high impedance 67 ??? ? 21.0 16.0 x ck i ck ns 89 fst input (bl, wr) setup time before sckt falling edge 5 ??2.0 18.0 ? ? x ck i ck ns 90 fst input (wl) setup time before sckt falling edge ? ? 2.0 18.0 ? ? x ck i ck ns 91 fst input hold time after sckt falling edge ? ? 4.0 5.0 ? ? x ck i ck ns 1 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that sckt and sckr are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that sckt and sckr are the same clock) 2 bl = bit length wl = word length wr = word length relative 3 sckt(sckt pin) = transmit clock sckr(sckr pin) = receive clock fst(fst pin) = transmit frame sync fsr(fsr pin) = receive frame sync hckt(hckt pin) = transmit high frequency clock hckr(hckr pin) = receive high frequency clock 4 for the internal clock, the external clock cycle is defined by icyc and the esai control register. 5 the word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the second-to-last bit clock of the first word in the frame. 6 periodically sampled and not 100% tested. table 42. enhanced serial audio interface timing (continued) no. characteristics 1,2 symbol expression 2 min. max. condition 3 unit
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 55 figure 32. esai transmitter timing see note sckt (input/output) fst (bit) out fst (word) out data out fst (bit) in fst (word) in note: in network mode, output flag transitions can occur at the start of each time slot within the frame. in normal mode, the output flag state is asserted for the entire frame period. 62 64 78 79 82 83 87 86 86 84 93 91 89 90 91 63 last bit first bit
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 56 figure 33. esai receiver timing 4.7.7 esdhcv2 ac electrical specifications figure 34 depicts the timing of esdhcv2, and table 43 lists the esdhcv2 timing characteristics. the following definitions apply to va lues and signals described in table 43 : ? ls: low-speed mode. low-speed card can tolerate a clock up to 400 khz. ? fs: full-speed mode. for a full-speed mmc card, the card clock can reach 20 mhz; a full-speed sd/sdio card can reach 25 mhz. ? hs: high-speed mode. for a high-speed mmc card, the card clock can reach 52 mhz; sd/sdio can reach 50 mhz. sckr (input/output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in 62 64 65 69 70 72 71 75 73 74 75 77 76 63 66 first bit last bit
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 57 figure 34. esdhcv2 timing table 43. esdhcv2 interface timing specification id parameter symbols min. max. unit card input clock sd1 clock frequency (low speed) f pp 1 1 in low-speed mode, the card clock must be lower than 400 khz, voltage ranges from 2.7 to 3.6 v. 0 400 khz clock frequency (sd/sdio full speed/high speed) f pp 2 2 in normal-speed mode for the sd/sdio card, clock frequency can be any value between 0?25 mhz. in high-speed mode, clock frequency can be any value between 0?50 mhz. 025/50mhz clock frequency (mmc full speed/high speed) f pp 3 3 in normal-speed mode for mmc card, clock frequency can be any value between 0 and 20 mhz. in high-speed mode, clock frequency can be any value between 0?52 mhz. 020/52mhz clock frequency (identification mode) f od 100 400 khz sd2 clock low time t wl 7?ns sd3 clock high time t wh 7?ns sd4 clock rise time t tlh ?3ns sd5 clock fall time t thl ?3ns esdhc output / card inputs cmd, dat (reference to clk) sd6 esdhc output delay t od ?3 3 ns esdhc input / card outputs cmd, dat (reference to clk) sd7 esdhc input setup time t isu 5?ns sd8 esdhc input hold time t ih 4 4 to satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. 2.5 ? ns sd1 sd3 sd5 sd4 sd7 sdhcx_cmd output from esdhcv2 to card sdhcx_dat_1 sdhcx_dat_7 sdhcx_dat_0 output from card to esdhcv2 sdhcx_clk sd2 sd8 sd6 sdhcx_cmd sdhcx_dat_1 sdhcx_dat_7 sdhcx_dat_0
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 58 4.7.8 fast ethernet controller (fec) ac electrical specifications this section describes the electrical information of the fec module. the fec is designed to support both 10- and 100-mbps ethernet networks. an external transceiver interface and transceiver function are required to complete the interface to the media. the fec supports the 10/100 mbps media independent interface (mii) using a total of 18 pins . the 10-mbps 7-wire interface that is restricted to a 10-mbps data rate uses seven of the mii pins for connection to an external ethernet transceiver. 4.7.8.1 fec ac timing this section describes the ac timing specifications of the fec. the mii signals are compatible with transceivers operating at a voltage of 3.3 v. 4.7.8.2 mii receive signal timing the mii receive timing signals consist of fec_rxd[3:0], fec_rx_dv, fec_rx_er, and fec_rx_clk. the receiver functions correctly up to a fec_rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requireme nt. additionally, the processor clock frequency must exceed twice the fec_rx_clk frequency. table 44 lists mii receive channel timings. 1 fec_rx_dv, fec_rx_clk, and fec_rxd0 have the same timing when in 10 mbps 7-wire interface mode. figure 35 shows the mii receive signal timings listed in table 44 . figure 35. mii receive signal timing diagram table 44. mii receive signal timing num characteristic 1 min. max. unit m1 fec_rxd[3:0], fec_rx_dv, fec_rx_er to fec_rx_clk setup 5 ? ns m2 fec_rx_clk to fec_rxd[3:0], fec_rx_dv, fec_rx_er hold 5 ? ns m3 fec_rx_clk pulse width high 35% 65% fec_rx_clk period m4 fec_rx_clk pulse width low 35% 65% fec_rx_clk period fec_rx_clk (input) fec_rxd[3:0] (inputs) fec_rx_dv fec_rx_er m3 m4 m1 m2
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 59 4.7.8.3 mii transmit signal timing the transmitter timing signals consist of fec_txd[3:0], fec_tx_en, fec_tx_er, and fec_tx_clk. the transmitter functions correctly up to a fec_tx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement . additionally, the processor clock frequency must exceed twice the fec_tx_clk frequency. table 45 lists mii transmit channel timings. 1 fec_tx_en, fec_tx_clk, and fec_txd0 have the same timing when in 10 mbps 7-wire interface mode. figure 36 shows the mii transmit signal timings listed in table 45 . figure 36. mii transmit signal timing diagram 4.7.8.4 mii asynchronous inputs signal timing the mii asynchronous timing signals are fec_crs and fec_col. table 46 lists mii asynchronous inputs signal timing. 1 fec_col has the same timing in 10 mbit 7-wire interface mode. table 45. mii transmit signal timing num characteristic 1 min. max. unit m5 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er invalid 5? ns m6 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er valid ?20 ns m7 fec_tx_clk pulse width high 35% 65% fec_tx_clk period m8 fec_tx_clk pulse width low 35% 65% fec_tx_clk period table 46. mii asynch inputs signal timing num characteristic min. max. unit m9 1 fec_crs to fec_col minimum pulse width 1.5 ? fec_tx_clk period fec_tx_clk (input) fec_txd[3:0] (outputs) fec_tx_en fec_tx_er m7 m8 m5 m6
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 60 figure 37 shows mii asynchronous input timings listed in table 46 . figure 37. mii asynch inputs timing diagram 4.7.8.5 mii serial management channel timing serial management channel timing is accomp lished using fec_mdio and fec_mdc. the fec functions correctly with a maximum mdc frequency of 2.5 mhz. table 47 lists mii serial management channel timings. the mdc frequency should be equal to or less than 2.5 mhz to be compliant with the ieee 802.3 mii specification. however the fec can function corr ectly with a maximum mdc frequency of 15 mhz. figure 38 shows mii serial management channel timings listed in table 47 . table 47. mii transmit signal timing num characteristic min. max. unit m10 fec_mdc falling edge to fec_mdio output invalid (minimum propagation delay) 0?ns m11 fec_mdc falling edge to fec_mdio output valid (max. propagation delay) ?5ns m12 fec_mdio (input) to fec_mdc rising edge setup 18 ? ns m13 fec_mdio (input) to fec_mdc rising edge hold 0 ? ns m14 fec_mdc pulse width high 40% 60% fec_mdc period m15 fec_mdc pulse width low 40% 60% fec_mdc period fec_crs, fec_col m9
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 61 figure 38. mii serial management channel timing diagram 4.7.9 fir electrical specifications fir implements asynchronous infrared protocols (fir, mir) defined by irda ? (infrared data association). refer to the irda website for details on fir and mir protocols. 4.7.10 flexcan module ac electrical specifications the electrical characteristics are related to the can transceiver outside the chip. for use in an application, the max3051 is recommended. for details, please re fer to the max3051 datasheetthe mcimx35 has two can modules available for systems design. tx and rx ports for both modules are multiplexed with other i/o pads. refer to the iomux chapter of the mcimx35 multimedia applications processor reference manual to see which pads expose tx and rx pins; these ports are named txcan and rxcan, respectively. 4.7.11 i 2 c ac electrical specifications this section describes the electrical information of the i 2 c module. 4.7.11.1 i 2 c module timing figure 39 depicts the timing of the i 2 c module. table 48 lists the i 2 c module timing parameters. fec_mdc (output) fec_mdio (output) m14 m15 m10 m11 m12 m13 fec_mdio (input)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 62 figure 39. i 2 c bus timing diagram table 48 . i 2 c module timing parameters id parameter standard mode fast mode unit min. max. min. max. ic1 i2clk cycle time 10 ? 2.5 ? s ic2 hold time (repeated) start condition 4.0 ? 0.6 ? s ic3 set-up time for stop condition 4.0 ? 0.6 ? s ic4 data hold time 0 1 1 a device must internally provide a hold time of at least 300 ns for the i2dat signal in order to bridge the undefined region of the falling edge of i2clk. 3.45 2 2 the maximum hold time has to be met only if the device does not stretch the low period (id ic6) of the i2clk signal. 0 1 0.9 2 s ic5 high period of i2clk clock 4.0 ? 0.6 ? s ic6 low period of the i2clk clock 4.7 ? 1.3 ? s ic7 set-up time for a repeated start condition 4.7 ? 0.6 ? s ic8 data set-up time 250 ? 100 3 3 a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement of set-up time (id ic7) of 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the i2clk signal. if such a device does stretch the low period of the i2clk signal, it must output the next data bit to the i2dat line max_rise_t ime (id no ic10) + data_setup_time (id no ic8) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the i2clk line is released. ?ns ic9 bus free time between a stop and start condition 4.7 ? 1.3 ? s ic10 rise time of both i2dat and i2clk signals ? 1000 ? 300 ns ic11 fall time of both i2dat and i2clk signals ? 300 ? 300 ns ic12 capacitive load for each bus line (c b ) ? 400 ? 400 pf ic10 ic11 ic9 ic2 ic8 ic4 ic7 ic3 ic6 ic10 ic5 ic11 start stop start start i2dat i2clk ic1
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 63 4.7.12 ipu?sensor interfaces 4.7.12.1 supported camera sensors table 49 lists the known supported camera sensors at the time of publication. 4.7.12.2 functional description there are three timing modes supported by the ipu. 4.7.12.2.4 pseudo bt.656 video mode smart camera sensors, which typically include image processing capability, support video mode transfer operations. they use an embedde d timing syntax to replace the sensb_vsync and sensb_hsync signals. the timing syntax is defined by the bt.656 standard. this operation mode follows the recommendations of the itu bt.656 specifications. the only control signal used is sensb_pix_clk. start-of-frame and active-line signals are embedded in the data stream. an active line starts with a sav code and ends with an eav code. in some cases, digital blanking is inserted in between eav and sav code. the csi decodes and filters out the timing coding from the data stream, thus recovering sensb_vsync and sensb_hsync signals for internal use. table 49. supported camera sensors 1 1 freescale semiconductor does not recommend one supplier over another and in no way suggests that these are the only camera suppliers. vendor model conexant cx11646, cx20490 2 , cx20450 2 2 these sensors have not been validated at the time of publication. agilant hdcp?2010, adcs?1021 2 , adcs?1021 2 toshiba tc90a70 icmedia icm202a, icm102 2 imagic im8801 transchip tc5600, tc5600j, tc5640, tc5700, tc6000 fujitsu mb86s02a micron mi-soc?0133 matsushita mn39980 stmicro w6411, w6500, w6501 2 , w6600 2 , w6552 2 , stv0974 2 omnivision ov7620, ov6630, ov2640 sharp lz0p3714 (ccd) motorola mc30300 (python) 2 , scm20014 2 , scm20114 2 , scm22114 2 , scm20027 2 national semiconductor lm9618 2
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 64 4.7.12.2.5 gated clock mode the sensb_vsync, sensb_hsync, and sensb_pix_clk signals are used in this mode. see figure 40 . figure 40. gated clock mode timing diagram a frame starts with a rising edge on sensb_vsync (a ll the timing corresponds to straight polarity of the corresponding signals). then sensb_hsync goes to hi gh and hold for the entire line. the pixel clock is valid as long as sensb_hsync is high. data is la tched at the rising edge of the valid pixel clocks. sensb_hsync goes to low at the end of the line. pi xel clocks then become invalid and the csi stops receiving data from the stream. for the next line, the sensb_hsync timing repeats. for the next frame, the sensb_vsync timing repeats. 4.7.12.2.6 non-gated clock mode the timing is the same as the gated-clock mode (described in section 4.7.12.2.5, ?gated clock mode ?), except for the sensb_hsync signal, which is not used. see figure 41 . all incoming pixel clocks are valid and will cause data to be latched into the i nput fifo. the sensb_pix_clk signal is inactive (states low) until valid data is going to be transmitted over the bus. figure 41. non-gated clock mode timing diagram sensb_vsync sensb_hsync sensb_pix_clk sensb_data[9:0] invalid 1st byte n+1th frame invalid 1st byte nth frame active line start of frame sensb_vsync sensb_pix_clk sensb_data[7:0] invalid 1st byte n+1th frame invalid 1st byte nth frame start of frame
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 65 the timing described in figure 41 is that of a motorola sensor. some other sensors may have slightly different timing. the csi can be programmed to support rising/falling-edge triggered sensb_vsync; active-high/low sensb_hsync; and rising/falling-edge triggered sensb_pix_clk. 4.7.12.3 electrical characteristics figure 42 depicts the sensor interface timing, and table 50 lists the timing parameters. figure 42. sensor interface timing diagram table 50. sensor interface timing parameters id parameter symbol min. max. units ip1 sensor input clock frequency fmck 0.01 133 mhz ip2 data and control setup time tsu 5 ? ns ip3 data and control holdup time thd 3 ? ns ip4 sensor output (pixel) clock frequency fpck 0.01 133 mhz sensb_mclk ip3 sensb_data, sensb_vsync, ip2 1/ip1 1/ip4 sensb_pix_clk (sensor input) (sensor output) sensb_hsync
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 66 4.7.13 ipu ? display interfaces 4.7.13.1 supported display components table 51 lists the known supported display components at the time of publication. table 51. supported display components 1 1 freescale semiconductor does not recommend one supplier over another and in no way suggests that these are the only display component suppliers. type vendor model tft displays (memory-less) sharp (hr-tft super mobile lcd family) lq035q7 db02, lm019lc1sxx samsung (qcif and qvga tft modules for mobile phones) lts180s1-hf1, lts180s3-hf1, lts350q1-pe1, lts350q1-pd1, lts220q1-he1 2 2 these display components have not been validated at the time of publication. toshiba (ltm series) ltm022p806 2 , ltm04c380k 2 , ltm018a02a 2 , ltm020p332 2 , ltm021p337 2 , ltm019p334 2 , ltm022a783 2 , ltm022a05zz 2 nec nl6448bc20-08e, nl8060bc31-27 display controllers epson s1d15xxx series, s1d19xxx series, s1d13713, s1d13715 solomon systech ssd1301 (oled), ssd1828 (ldcd) hitachi hd66766, hd66772 ati w2300 smart display modules epson l1f10043 t 2 , l1f10044 t 2 , l1f10045 t 2 , l2d22002 2 , l2d20014 2 , l2f50032 2 , l2d25001 t 2 hitachi 120 160 65k/4096 c-stn (#3284 ltd-1398-2) based on hd 66766 controller densitron europe ltd all displays with mpu 80/68k series interface and serial peripheral interface sharp lm019lc1sxx sony acx506akm digital video encoders (for tv) analog devices adv7174/7179 crystal (cirrus logic) cs49xx series focus fs453/4
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 67 4.7.13.2 synchronous interfaces 4.7.13.2.7 interface to active matrix tft lcd panels, functional description figure 43 depicts the lcd interface timing for a generic ac tive matrix color tft panel. in this figure, signals are shown with negative polarity. the sequence of events for active matrix interface timing is as follows: ? dispb_d3_clk latches data into the panel on its negative edge (when positive polarity is selected). in active mode, dispb_d3_clk runs continuously. ? dispb_d3_hsync causes the panel to start a new line. ? dispb_d3_vsync causes the panel to start a ne w frame. it always encompasses at least one hsync pulse. ? dispb_d3_drdy acts like an output enable signal to the crt display. this output enables the data to be shifted to the display. when disabled, the data is invalid and the trace is off. figure 43. interface timing diagram for tft (active matrix) panels 4.7.13.2.8 interface to active matrix tft lcd panels, electrical characteristics figure 44 depicts the horizontal timing (timing of one line) , including both the horizontal sync pulse and the data. all figure parameters shown are programma ble. the timing images correspond to inverse polarity of the dispb_d3_clk signal and active-low polarity of the dispb_d3_hsync, dispb_d3_vsync and dispb_d3_drdy signals. dispb_d3_clk 123 m m-1 dispb_d3_hsync dispb_d3_vsync dispb_d3_hsync line 1 line 2 line 3 line 4 line n-1 line n dispb_d3_drdy dispb_d3_data
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 68 figure 44. tft panels timing diagram?horizontal sync pulse figure 45 depicts the vertical timing (timing of one frame). all figure parameters shown are programmable. figure 45. tft panels timing diagram?vertical sync pulse table 52 shows timing parameters of signals presented in figure 44 and figure 45 . table 52. synchronous display interface timing parameters?pixel level id parameter symbol value units ip5 display interface clock period tdicp tdicp 1 ns ip6 display pixel clock period tdpcp (disp3_if_clk_cnt_d+1) * tdicp ns ip7 screen width tsw (screen_width+1) * tdpcp ns ip8 hsync width thsw (h_sync_width+1) * tdpcp ns ip9 horizontal blank interval 1 thbi1 bgxp * tdpcp ns ip10 horizontal blank interval 2 thbi2 (screen_width?bgxp?fw) * tdpcp ns dispb_d3_hsync dispb_d3_drdy dispb_d3_data dispb_d3_clk ip7 ip9 ip10 ip8 start of line ip5 ip6 ip14 dispb_d3_vsync dispb_d3_hsync dispb_d3_drdy start of frame end of frame ip12 ip15 ip13 ip11
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 69 figure 46 depicts the synchronous display in terface timing for access level, and table 53 lists the timing parameters. the disp3_if_clk_down_wr and disp3_if_clk_up_wr parameters are set via the di_disp3_time_conf register. figure 46. synchronous display interface timing diagram?access level ip11 hsync delay thsd h_sync_delay * tdpcp ns ip12 screen height tsh (screen_height+1) * tsw ns ip13 vsync width tvsw if v_sync_width_l = 0 than (v_sync_width+1) * tdpcp else (v_sync_width+1) * tsw ns ip14 vertical blank interval 1 tvbi1 bgyp * tsw ns ip15 vertical blank interval 2 tvbi2 (screen_height ? bgyp ? fh) * tsw ns 1 display interface clock period immediate value display interface clock period average value. table 52. synchronous display interface timing parameters?pixel level (continued) id parameter symbol value units tdicp t hsp_clk disp3_if_clk_per_wr hsp_clk_period ----------------------------------------------------------------- - ? = ip19 dispb_d3_clk dispb_data ip18 ip20 dispb_d3_vsync ip17 ip16 dispb_d3_drdy dispb_d3_hsync other controls
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 70 4.7.13.3 interface to sharp hr-tft panels figure 47 depicts the sharp hr-tft panel interface timing, and table 54 lists the timing parameters. the cls_rise_delay, cls_fall_delay, ps_fall_delay, ps_rise_delay, rev_toggle_delay parameters are defined in the sdc_sharp_conf_1 and sdc_sharp_conf_2 registers. for other sharp interface timing characteristics, refer to section 4.7.13.2.8, ?interface to active matrix tft lcd panels, electrical characteristics.? the timing images correspond to straight polarity of the sharp signals. table 53. synchronous display interface timing parameters?access level id parameter symbol min. typ. 1 1 the exact conditions not have been finalized, but will likely match the current customer requirement for their specific display . these conditions may be device specific. max. units ip16 display interface clock low time tckl tdicd-tdicu-1.5 tdicd 2 -tdicu 3 2 display interface clock down time 3 display interface clock up time where ceil(x) rounds the elements of x to the nearest integers toward infinity. tdicd-tdicu+1.5 ns ip17 display interface clock high time tckh tdicp-tdicd+tdicu-1.5 tdicp-tdicd+tdicu tdicp-tdicd+tdicu+1.5 ns ip18 data setup time tdsu tdicd-3.5 tdicu ? ns ip19 data holdup time tdhd tdicp-tdicd-3.5 tdicp-tdicu ? ns ip20 control signals setup time to display interface clock tcsu tdicd-3.5 tdicu ? ns tdicd 1 2 -- -t hsp_clk ceil 2 disp3_if_clk_down_wr ? hsp_clk_period -------------------------------------------------------------------------------- - ? = tdicu 1 2 -- -t hsp_clk ceil 2 disp3_if_clk_up_wr ? hsp_clk_period --------------------------------------------------------------------- - ? =
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 71 figure 47. sharp hr-tft panel interface timing diagram?pixel level 4.7.13.4 synchronous interface to dual-port smart displays functionality and electrical characteristics of the synchronous interface to dual-port smart displays are identical to parameters of the synchronous interface. see section 4.7.13.2.8, ?interface to active matrix tft lcd panels, electrical characteristics.? table 54. sharp synchronous display interface timing parameters?pixel level id parameter symbol value units ip21 spl rise time tsplr (bgxp ? 1) * tdpcp ns ip22 cls rise time tclsr cls_rise_delay * tdpcp ns ip23 cls fall time tclsf cls_fall_delay * tdpcp ns ip24 cls rise and ps fall time tpsf ps_fall_delay * tdpcp ns ip25 ps rise time tpsr ps_rise_delay * tdpcp ns ip26 rev toggle time trev rev_toggle_delay * tdpcp ns d1 d2 dispb_d3_clk dispb_d3_data dispb_d3_spl dispb_d3_hsync dispb_d3_cls dispb_d3_ps dispb_d3_rev 1 dispb_d3_clk period ip26 d320 horizontal timing ip22 ip23 ip25 ip21 ip24 example is drawn with fw+1=320 pixel/line, fh+1=240 lines. spl pulse width is fixed and aligned to the first data of the line. rev toggles every hsync period.
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 72 4.7.13.4.9 interface to a tv encoder?functional description the interface has an 8-bit data bus, transferring a single 8-bit value (y/u/v) in each cycle. the bits d7?d0 of the value are mapped to bits ld17?ld10 of the data bus, respectively. figure 48 depicts the interface timing. ? the frequency of the clock dispb_d3_clk is 27 mhz. ? the dispb_d3_hsync, dispb_d3_vsync a nd dispb_d3_drdy signals are active low. ? the transition to the next row is marked by th e negative edge of the dispb_d3_hsync signal. it remains low for a single clock cycle. ? the transition to the next field/frame is marked by the negative edge of the dispb_d3_vsync signal. it remains low for at least one clock cycle. ? at a transition to an odd field (of the next frame), the negative edges of dispb_d3_vsync and dispb_d3_hsync coincide. ? at a transition to an even field (of the same frame), they do not coincide. ? the active intervals?during which data is transferred?are marked by the dispb_d3_hsync signal being high.
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 73 figure 48. tv encoder interface timing diagram dispb_d3_clk dispb_d3_hsync dispb_data dispb_d3_vsync cb y cr cb y cr y pixel data timing line and field timing - ntsc even field odd field odd field even field 624 621 311 308 line and field timing - pal dispb_d3_hsync dispb_d3_drdy dispb_d3_vsync dispb_d3_hsync dispb_d3_drdy dispb_d3_vsync even field odd field odd field even field 1 523 262 261 dispb_d3_drdy dispb_d3_hsync dispb_d3_drdy dispb_d3_vsync dispb_d3_hsync dispb_d3_vsync 524 525 2 3 4 10 263 264 265 266 267 268 269 273 622 623 625 1 2 23 309 310 312 313 314 336 56 34 316 315 dispb_d3_drdy
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 74 4.7.13.4.10 interface to a tv encoder, electrical characteristics the timing characteristics of the tv encoder interface are identical to the synchronous display characteristics. see section 4.7.13.2.8, ?interface to active matrix tft lcd panels, electrical characteristics.? 4.7.13.5 asynchronous interfaces 4.7.13.5.11 parallel interfaces, functional description the ipu supports the following asynchronous parallel interfaces: ? system 80 interface ? type 1 (sampling with the chip select signal) with and without byte enable signals. ? type 2 (sampling with the read and write si gnals) with and without byte enable signals. ? system 68k interface ? type 1 (sampling with the chip select signal) with or without byte enable signals. ? type 2 (sampling with the read and write si gnals) with or without byte enable signals. for each of four system interfaces, there are three burst modes: 1. burst mode without a separate clock?the burst length is defined by the corresponding parameters of the idmac (when data is transferred from the system memory) or by the hburst signal (when the mcu directly accesses the display via the slave ahb bus). for system 80 and system 68k type 1 interfaces, data is sampled by the cs signal and other control si gnals changes only when transfer direction is changed during the burst. for type 2 interfaces, data is sampled by the wr/rd signals (system 80) or by the enable signal (s ystem 68k), and the cs signal stays active during the whole burst. 2. burst mode with the separate clock dispb_bclk?in this mode, data is sampled with the dispb_bclk clock. the cs signal stays active during whole burst transfer. other controls are changed simultaneously with data when the bus state (read, write or wait) is altered. the cs signals and other controls m ove to non-active state after burst has been completed. 3. single access mode?in this mode, slave ahb and dma burst are broken to single accesses. the data is sampled with cs or other controls acco rding to the interface type as described above. all controls (including cs) become non-active for one display interface clock after each access. this mode corresponds to the ati single access mode. both system 80 and system 68k interfaces are supported for all described modes as depicted in figure 49 , figure 50 , figure 51 , and figure 52 . these timing images correspond to active-low dispb_d n _cs, dispb_d n _wr and dispb_d n _rd signals. additionally, the ipu allows a programmable pause between two bursts. the pause is defined in the hsp_clk cycles. it allows the prevention of timing violation between two sequential bursts or two accesses to different displays. the range of this pause is from 4 to 19 hsp_clk cycles.
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 75 figure 49. asynchronous parallel system 80 interface (type 1) burst mode timing diagram dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_bclk dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data burst access mode with sampling by cs signal burst access mode with sampling by separate burst clock (bclk) single access mode (all control signals are not active for one display interface clock after each display access)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 76 figure 50. asynchronous parallel system 80 interface (type 2) burst mode timing diagram dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_bclk dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data burst access mode with sampling by wr/rd signals burst access mode with sampling by separate burst clock (bclk) single access mode (all control signals are not active for one display interface clock after each display access)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 77 figure 51. asynchronous parallel system 68k interface (type 1) burst mode timing diagram dispb_d#_cs dispb_wr dispb_rd dispb_data dispb_bclk dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_d#_cs dispb_wr dispb_rd dispb_data (read/write) (enable) dispb_par_rs dispb_par_rs (read/write) (enable) (read/write) (enable) burst access mode with sampling by cs signal burst access mode with sampling by separate burst clock (bclk) single access mode (all control signals are not active for one display interface clock after each display access)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 78 figure 52. asynchronous parallel system 68k interface (type 2) burst mode timing diagram display read operation can be performed with wait states when each read access takes up to 4 display interface clock cycles according to the disp0_rd_wait_st parameter in the dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_bclk dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data (read/write) (enable) (read/write) (enable) (read/write) (enable) burst access mode with sampling by enable signal burst access mode with sampling by separate burst clock (bclk) single access mode (all control signals are not active for one display interface clock after each display access)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 79 di_disp0_time_conf_3, di_disp1_time_conf_3, di_disp2_time_conf_3 registers. figure 53 shows timing of the parallel interface with read wait states. figure 53. parallel interface timing diagram?read wait states 4.7.13.5.12 parallel interfaces, electrical characteristics figure 54 , figure 56 , figure 55 , and figure 57 depict timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces. table 55 lists the timing parameters at display access level. all write operation read operation dispb_d#_cs dispb_rd dispb_wr dispb_par_rs dispb_d#_cs dispb_rd dispb_wr dispb_par_rs dispb_data dispb_d#_cs dispb_rd dispb_wr dispb_par_rs dispb_data dispb_data disp0_rd_wait_st=00 disp0_rd_wait_st=01 disp0_rd_wait_st=10
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 80 timing images are based on active low control si gnals (signal polarity is controlled via the di_disp_sig_pol register). figure 54. asynchronous parallel system 80 interface (type 1) timing diagram ip28, ip27 read data ip32, ip30 ip37 ip38 dispb_par_rs dispb_data dispb_data dispb_wr (write_l) (input) (output) ip35, ip33 ip36, ip34 ip31, ip29 ip40 ip39 ip46,ip44 ip47 ip45, ip43 ip42, ip41 dispb_rd (read_l) dispb_d#_cs dispb_data[16] dispb_data[17] read point (write_h) (read_h)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 81 figure 55. asynchronous parallel system 80 interface (type 2) timing diagram ip28, ip27 read data ip32, ip30 dispb_par_rs dispb_data dispb_data dispb_wr (write_l) (input) (output) ip36, ip34 ip31, ip29 ip40 ip39 ip47 ip45, ip43 ip42, ip41 dispb_rd (read_l) dispb_d#_cs dispb_data[16] dispb_data[17] (write_h) (read_h) ip38 ip35, ip33 ip37 read point ip46,ip44
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 82 figure 56. asynchronous parallel system 68k interface (type 1) timing diagram ip28, ip27 read data ip32, ip30 ip37 ip38 dispb_par_rs dispb_data dispb_data dispb_wr (input) (output) ip35,ip33 ip36, ip34 ip31, ip29 ip40 ip39 ip47 ip45, ip43 ip42, ip41 dispb_rd (enable_l) dispb_d#_cs (read/write) dispb_data[17] (enable_h) read point ip46,ip44
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 83 figure 57. asynchronous parallel system 68k interface (type 2) timing diagram table 55. asynchronous parallel interface timing parameters?access level id parameter symbol min. typ. 1 max. units ip27 read system cycle time tcycr tdicpr-1.5 tdicpr 2 tdicpr+1.5 ns ip28 write system cycle time tcycw tdicpw-1.5 tdicpw 3 tdicpw+1.5 ns ip29 read low pulse width trl tdicdr-tdicur-1.5 tdicdr 4 -tdicur 5 tdicdr-tdicur+1.5 ns ip30 read high pulse width trh tdicpr-tdicdr+tdicur-1.5 tdicpr-tdicdr+ tdicur tdicpr-tdicdr+tdicur+1.5 ns ip31 write low pulse width twl tdicdw-tdicuw-1.5 tdicdw 6 -tdicuw 7 tdicdw-tdicuw+1.5 ns ip32 write high pulse width twh tdicpw-tdicdw+ tdicuw-1.5 tdicpw-tdicdw+ tdicuw tdicpw-tdicdw+ tdicuw+1.5 ns ip33 controls setup time for read tdcsr tdicur-1.5 tdicur ? ns ip34 controls hold time for read tdchr tdicpr-tdicdr-1.5 tdicpr-tdicdr ? ns ip35 controls setup time for write tdcsw tdicuw-1.5 tdicuw ? ns ip28, ip27 read data ip32, ip30 ip37 ip38 dispb_par_rs dispb_data dispb_data dispb_wr (input) (output) ip35,ip33 ip36, ip34 ip31, ip29 ip40 ip39 ip45, ip43 ip42, ip41 dispb_rd (enable_l) dispb_d#_cs (read/write) dispb_data[17] (enable_h) read point ip46,ip44 ip47
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 84 ip36 controls hold time for write tdchw tdicpw-tdicdw-1.5 tdicpw-tdicdw ? ns ip37 slave device data delay 8 tr a c c 0 ? t d r p 9 -tlbd 10 -tdicur-1.5 ns ip38 slave device data hold time 8 troh tdrp-tlbd-tdicdr+1.5 ? tdicpr-tdicdr-1.5 ns ip39 write data setup time tds tdicdw-1.5 tdicdw ? ns ip40 write data hold time tdh tdicpw-tdicdw-1.5 tdicpw-tdicdw ? ns ip41 read period 2 tdicpr tdicpr-1.5 tdicpr tdicpr+1.5 ns ip42 write period 3 tdicpw tdicpw-1.5 tdicpw tdicpw+1.5 ns ip43 read down time 4 tdicdr tdicdr-1.5 tdicdr tdicdr+1.5 ns ip44 read up time 5 tdicur tdicur-1.5 tdicur tdicur+1.5 ns ip45 write down time 6 tdicdw tdicdw-1.5 tdicdw tdicdw+1.5 ns ip46 write up time 7 tdicuw tdicuw-1.5 tdicuw tdicuw+1.5 ns ip47 read time point 9 tdrp tdrp-1.5 tdrp tdrp+1.5 ns 1 the exact conditions have not been finalized, but will likely match the current customer requirement for their specific display . these conditions may be device-specific. 2 display interface clock period value for read: 3 display interface clock period value for write: 4 display interface clock down time for read: 5 display interface clock up time for read: 6 display interface clock down time for write: 7 display interface clock up time for write: 8 this parameter is a requirement to the display connected to the ipu 9 data read point 10 loopback delay tlbd is the cumulative propagation delay of read controls and read data. it includes an ipu output delay, a device-level output delay, board delays, a device-level input delay, an ipu input delay. this value is device specific. table 55. asynchronous parallel interface timing parameters?access level (continued) id parameter symbol min. typ. 1 max. units tdicpr t hsp_clk ceil ? disp#_if_clk_per_rd hsp_clk_period ---------------------------------------------------------------- = tdicpw t hsp_clk ceil ? disp#_if_clk_per_wr hsp_clk_period ----------------------------------------------------------------- - = tdicdr 1 2 -- -t hsp_clk ceil 2 disp#_if_clk_down_rd ? hsp_clk_period ------------------------------------------------------------------------------- ? = tdicur 1 2 -- -t hsp_clk ceil 2 disp#_if_clk_up_rd ? hsp_clk_period -------------------------------------------------------------------- ? = tdicdw 1 2 -- -t hsp_clk ceil 2 disp#_if_clk_down_wr ? hsp_clk_period -------------------------------------------------------------------------------- - ? = tdicuw 1 2 -- -t hsp_clk ceil 2 disp#_if_clk_up_wr ? hsp_clk_period --------------------------------------------------------------------- - ? = tdrp t hsp_clk ceil disp#_read_en hsp_clk_period -------------------------------------------------- ? =
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 85 the disp#_if_clk_per_wr, disp#_if_clk_per_rd, hsp_clk_period, disp#_if_clk_down_wr, disp#_if_clk_up_wr, disp#_if_clk_down_rd, disp#_if_clk_up_rd and disp#_read_en parameters are programmed via the di_disp#_time_conf_1, di_disp#_time_conf_2 and di_hsp_clk_per registers. 4.7.13.6 serial interfaces, functional description the ipu supports the following types of asynchronous serial interfaces: ? 3-wire (with bidirectional data line) ? 4-wire (with separate data input and output lines) ? 5-wire type 1 (with sampling rs by the serial clock) ? 5-wire type 2 (with sampling rs by the chip select signal) figure 58 depicts timing of the 3-wire serial interf ace. the timing images correspond to active-low dispb_d#_cs signal and the straight polarity of the dispb_sd_d_clk signal. for this interface, a bidirectional data line is used outside the device. the ipu still uses separate input and output data lines (ipp_ind_dispb_sd_d and ipp_do_dispb_sd_d). the i/o mux should provide joining the internal data lines to the bidirectional external line according to the ipp_obe_dispb_sd_d signal provided by the ipu. each data transfer can be preceded by an optional preamble with programmable length and contents. the preamble is followed by read/write (rw) and address (rs) bits. the order of the these bits is programmable. the rw bit can be disabled. the follo wing data can consist of one word or of a whole burst. the interface parameters are controlled by the di_ser_disp1_conf and di_ser_disp2_conf registers. figure 58. 3-wire serial interface timing diagram figure 59 depicts timing of the 4-wire serial interface. for this interface, there are separate input and output data lines both inside and outside the device. preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw rs input or output data d7 d6 d5 d4 d3 d2 d1 d0 1 display if clock cycle 1 display if clock cycle
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 86 figure 59. 4-wire serial interface timing diagram figure 60 depicts timing of the 5-wire serial interface (type 1). for this interface, a separate rs line is added. when a burst is transmitted within a single active chip select interval, the rs can be changed at boundaries of words. preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw rs output data d7 d6 d5 d4 d3 d2 d1 d0 dispb_sd_d (output) (input) preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw rs input data dispb_sd_d d7 d6 d5 d4 d3 d2 d1 d0 (output) (input) write read 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 87 figure 60. 5-wire serial interface (type 1) timing diagram figure 61 depicts timing of the 5-wire serial interface (type 2). for this interface, a separate rs line is added. when a burst is transmitted within a single active chip select interval, the rs can be changed at boundaries of words. preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw d7 d6 d5 d4 d3 d2 d1 d0 dispb_sd_d (output) (input) dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw dispb_sd_d d7 d6 d5 d4 d3 d2 d1 d0 (output) (input) write read dispb_ser_rs dispb_ser_rs 1 display if clock cycle 1 display if clock cycle output data 1 display if clock cycle 1 display if clock cycle preamble input data
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 88 figure 61. 5-wire serial interface (type 2) timing diagram 4.7.13.6.13 serial interfaces, electrical characteristics figure 62 depicts timing of the serial interface. table 56 lists the timing parameters at display access level. preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw output data d7 d6 d5 d4 d3 d2 d1 d0 dispb_sd_d (output) (input) preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw input data dispb_sd_d d7 d6 d5 d4 d3 d2 d1 d0 (output) (input) write read dispb_ser_rs dispb_ser_rs 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 89 figure 62. asynchronous serial interface timing diagram table 56. asynchronous serial interface timing parameters?access level id parameter symbol min. typ. 1 max. units ip48 read system cycle time tcycr tdicpr-1.5 tdicpr 2 tdicpr+1.5 ns ip49 write system cycle time tcycw tdicpw-1.5 tdicpw 3 tdicpw+1.5 ns ip50 read clock low pulse width trl tdicdr-tdicur-1.5 tdicdr 4 -tdicur 5 tdicdr-tdicur+1.5 ns ip51 read clock high pulse width trh tdicpr-tdicdr+tdicur-1.5 tdicpr-tdicdr+ tdicur tdicpr-tdicdr+tdicur+1.5 ns ip52 write clock low pulse width twl tdicdw-tdicuw-1.5 tdicdw 6 -tdicuw 7 tdicdw-tdicuw+1.5 ns ip53 write clock high pulse width twh tdicpw-tdicdw+ tdicuw-1.5 tdicpw-tdicdw+ tdicuw tdicpw-tdicdw+ tdicuw+1.5 ns ip54 controls setup time for read tdcsr tdicur-1.5 tdicur ? ns ip55 controls hold time for read tdchr tdicpr-tdicdr-1.5 tdicpr-tdicdr ? ns ip56 controls setup time for write tdcsw tdicuw-1.5 tdicuw ? ns ip57 controls hold time for write tdchw tdicpw-tdicdw-1.5 tdicpw-tdicdw ? ns ip49, ip48 read data ip51, ip53 ip58 ip59 dispb_ser_rs dispb_data dispb_data (input) (output) ip56,ip54 ip57, ip55 ip50, ip52 ip61 ip60 ip67,ip65 ip47 ip64, ip66 ip62, ip63 dispb_sd_d_clk read point
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 90 ip58 slave device data delay 8 tracc 0 ? tdrp 9 -tlbd 10 -tdicur-1.5 ns ip59 slave device data hold time 8 troh tdrp-tlbd-tdicdr+1.5 ? tdicpr-tdicdr-1.5 ns ip60 write data setup time tds tdicdw-1.5 tdicdw ? ns ip61 write data hold time tdh tdicpw-tdicdw-1.5 tdicpw-tdicdw ? ns ip62 read period 2 tdicpr tdicpr-1.5 tdicpr tdicpr+1.5 ns ip63 write period 3 tdicpw tdicpw-1.5 tdicpw tdicpw+1.5 ns ip64 read down time 4 tdicdr tdicdr-1.5 tdicdr tdicdr+1.5 ns ip65 read up time 5 tdicur tdicur-1.5 tdicur tdicur+1.5 ns ip66 write down time 6 tdicdw tdicdw-1.5 tdicdw tdicdw+1.5 ns ip67 write up time 7 tdicuw tdicuw-1.5 tdicuw tdicuw+1.5 ns ip68 read time point 9 tdrp tdrp-1.5 tdrp tdrp+1.5 ns 1 the exact conditions have not been finalized, but will likely match the current customer requirement for their specific display . these conditions may be device specific. 2 display interface clock period value for read: 3 display interface clock period value for write: 4 display interface clock down time for read: 5 display interface clock up time for read: 6 display interface clock down time for write: 7 display interface clock up time for write: 8 this parameter is a requirement to the display connected to the ipu. 9 data read point: 10 loopback delay tlbd is the cumulative propagation delay of read controls and read data. it includes an ipu output delay, a device-level output delay, board delays, a device-level input delay, and an ipu input delay. this value is device specific. table 56. asynchronous serial interface timing parameters?access level (continued) id parameter symbol min. typ. 1 max. units tdicpr t hsp_clk ceil ? disp#_if_clk_per_rd hsp_clk_period ---------------------------------------------------------------- = tdicpw t hsp_clk ceil ? disp#_if_clk_per_wr hsp_clk_period ----------------------------------------------------------------- - = tdicdr 1 2 -- -t hsp_clk ceil 2 disp#_if_clk_down_rd ? hsp_clk_period ------------------------------------------------------------------------------- ? = tdicur 1 2 -- -t hsp_clk ceil 2 disp#_if_clk_up_rd ? hsp_clk_period -------------------------------------------------------------------- ? = tdicdw 1 2 -- -t hsp_clk ceil 2 disp#_if_clk_down_wr ? hsp_clk_period -------------------------------------------------------------------------------- - ? = tdicuw 1 2 -- -t hsp_clk ceil 2 disp#_if_clk_up_wr ? hsp_clk_period --------------------------------------------------------------------- - ? = tdrp t hsp_clk ceil disp#_read_en hsp_clk_period -------------------------------------------------- ? =
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 91 the disp#_if_clk_per_wr, disp#_if_clk_per_rd, hsp_clk_period, disp#_if_clk_down_wr, disp#_if_clk_up_wr, disp#_if_clk_down_rd, disp#_if_clk_up_rd and disp#_read_en parameters are programmed via the di_disp#_time_conf_1, di_disp#_time_conf_2 and di_hsp_clk_per registers. 4.7.14 memory stick host controller (mshc) figure 63 , figure 64 , and figure 65 depict the mshc timings, and table 57 and table 58 list the timing parameters. figure 63. mshc_clk timing diagram figure 64. transfer operation timing diagram (serial) tsclkwh tsclkwl tsclkc tsclkr tsclkf mshc_sclk tsclkc mshc_sclk tbssu tbsh tdsu tdh mshc_bs mshc_data (output) tdd mshc_data (intput)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 92 figure 65. transfer operation timing diagram (parallel) note the memory stick host controller is designed to meet the timing requirements per sony's memory stick pro format specifications . tables in this section detail the specifications? requirements for parallel and serial modes, and not the i.mx35 timing. table 57. serial interface timing parameters 1 signal parameter symbol standards unit min. max. mshc_sclk cycle tsclkc 50 ? ns h pulse length tsclkwh 15 ? ns l pulse length tsclkwl 15 ? ns rise time tsclkr ? 10 ns fall time tsclkf ? 10 ns mshc_bs setup time tbssu 5 ? ns hold time tbsh 5 ? ns tsclkc mshc_sclk tbssu tbsh tdsu tdh mshc_bs mshc_data (output) tdd mshc_data (input)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 93 4.7.15 medialb controller electrical specifications this section describes the electrical in formation of the medialb controller module. 4.7.15.1 medialb device ac timing figure 66 and figure 67 show the timing of medialb controller, and table 59 lists the medialb controller timing characteristics. medialb controllers configured as timing slaves use the most network as the pll clocking source during normal operation; however, brief periods of unlock can occur. during these periods of network unlock, the pll clocking source is switched to a local external crystal until the network relocks. the pll is temporarily unlocked during these periods of switching between the network and the crystal. specifications shown are applicable when the pll is locked, unless otherwise specified. mshc_data setup time tdsu 5 ? ns hold time tdh 5 ? ns output delay time tdd ? 15 ns 1 timing is guaranteed for nvcc from 2.7 v through 3.1 v and up to a maximum overdrive nvcc of 3.3 v. see nvcc restrictions described in ta ble 5 8 . table 58. parallel interface timing parameters 1 1 timing is guaranteed for nvcc from 2.7 v through 3.1 v and up to a maximum overdrive nvcc of 3.3 v. see nvcc restrictions described in table 8, "mcimx35 operating ranges," on page 13 . signal parameter symbol standards unit min. max. mshc_sclk cycle tsclkc 25 ? ns h pulse length tsclkwh 5 ? ns l pulse length tsclkwl 5 ? ns rise time tsclkr ? 10 ns fall time tsclkf ? 10 ns mshc_bs setup time tbssu 8 ? ns hold time tbsh 1 ? ns mshc_data setup time tdsu 8 ? ns hold time tdh 1 ? ns output delay time tdd ? 15 ns table 57. serial interface timing parameters 1 (continued) signal parameter symbol standards unit min. max.
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 94 figure 66. medialb timing figure 67. medialb pulse width variation timing ground = 0.0v; load capacitance = 60pf; medial b speed = 256/512fs; fs = 48 khz; all timing parameters specified from the valid voltage thre shold as listed below; unless otherwise noted. table 59. mlb 256/512fs timing parameters parameter symbol min typ max units comment mlbclk operating frequency 1 f mck 11.264 12.288 24.576 24.6272 25.600 mhz min: 256*fs at 44.0 khz typ: 256*fs at 48.0 khz typ: 512*fs at 48.0 khz max: 512*fs at 48.1 khz max: 512*fs pll unlocked mlbclk rise time t mckr 3ns v il to v ih mlb fall time t mckf 3ns v ih to v il mlbclk cycle time t mckc 81 40 ns 256*fs 512*fs
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 95 ground = 0.0v; load capacitance = 40pf; medialb speed = 1024fs; fs = 48 khz; all timing parameters specified from the valid voltage threshold as listed below; unless otherwise noted. mlbclk low time t mckl 31.5 30 37 35.5 ns 256*fs 256*fs pll unlocked 14.5 14 17 16.5 ns 512*fs 512*fs pll unlocked mlbclk high time t mckh 31.5 30 38 36.5 ns 256*fs 256*fs pll unlocked 14.5 14 17 16.5 ns 512*fs 512*fs pll unlocked mlbclk pulse width variation t mpwv 2ns pp note 2 mlbsig/mlbdat input valid to mlbclk falling t dsmcf 1ns mlbsig/mlbdat input hold from mlbclk low t dhmcf 0ns mlbsig/mlbdat output high impedance from mlbclk low t mcfdz 0t mckl ns bus hold time t mdzh 4nsnote 3 1 the mlb controller can shut off mlbclk to place medialb in a low-power state. 2 pulse width variattion is measured at 1.25v by triggering on one edge of mlbclk and measuring the spread on the other edge, measured in ns peak-to-peak (pp) 3 the board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for thi s time period. therefore, coupling must be minimized while meeting the maximum capacitive load listed. table 60. mlb device 1024fs timing parameters parameter symbol min typ max units comment mlbclk operating frequency 1 f mck 45.056 49.152 49.2544 51.200 mhz min: 1024*fs at 44.0 khz typ: 1024*fs at 48.0 khz max: 1024fs*fs at 48.1 khz max: 1024*fs pll unlocked mlbclk rise time t mckr 1ns v il to v ih mlb fall time t mckf 1ns v ih to v il mlbclk cycle time t mckc 20.3 ns mlbclk low time t mckl 6.5 6.1 7.7 7.3 ns pll unlocked mlbclk high time t mckh 9.7 9.3 10.6 10.2 ns pll unlocked mlbclk pulse width variation t mpwv 0.7 ns pp note 2 table 59. mlb 256/512fs timing parameters (continued) parameter symbol min typ max units comment
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 96 4.7.16 1-wire timing specifications figure 68 depicts the rpp timing, and table 61 lists the rpp timing parameters. figure 68. reset and presence pulses (rpp) timing diagram mlbsig/mlbdat input valid to mlbclk falling t dsmcf 1ns mlbsig/mlbdat input hold from mlbclk low t dhmcf 0ns mlbsig/mlbdat output high impedance from mlbclk low t mcfdz 0t mckl ns bus hold time t mdzh 2nsnote 3 1 the mlb controller can shut off mlbclk to place medialb in a low-power state. 2 pulse width variattion is measured at 1.25v by triggering on one edge of mlbclk and measuring the spread on the other edge, measured in ns peak-to-peak (pp) 3 the board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for thi s time period. therefore, coupling must be minimized while meeting the maximum capacitive load listed. table 61. rpp sequence delay comparisons timing parameters id parameters symbol min. typ. max. units ow1 reset time low t rstl 480 511 ? s ow2 presence detect high t pdh 15 ? 60 s ow3 presence detect low t pdl 60 ? 240 s ow4 reset time high t rsth 480 512 ? s table 60. mlb device 1024fs timing parameters (continued) parameter symbol min typ max units comment 1-wire bus ds2502 tx ?presence pulse? (batt_line) 1-wire tx ?reset pulse? ow1 ow2 ow3 ow4
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 97 figure 69 depicts write 0 sequence timing, and table 62 lists the timing parameters. figure 69. write 0 sequence timing diagram figure 70 shows write 1 sequence timing, figure 71 depicts the read sequence timing, and table 63 lists the timing parameters. figure 70. write 1 sequence timing diagram figure 71. read sequence timing diagram 4.7.17 parallel ata module ac electrical specifications the parallel ata module can work on pio/multiword dma/ultra-dma transfer modes. each transfer mode has a different data transfer rate, ultra dm a mode 4 data transfer rate is up to 100 mbps. table 62. wr0 sequence timing parameters id parameter symbol min. typ. max. units ow5 write 0 low time t wr0_low 60 100 120 s ow6 transmission time slot t slot ow5 117 120 s table 63. wr1 /rd timing parameters id parameter symbol min. typ. max. units ow7 write 1 / read low time t low1 1515s ow8 transmission time slot t slot 60 117 120 s ow9 release time t release 15 ? 45 s ow5 ow6 1-wire bus (batt_line) ow7 ow8 1-wire bus (batt_line) ow7 ow8 ow9 1-wire bus (batt_line)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 98 the parallel ata module interface consists of a total of 29 pins. some pins act on different function in different transfer mode. there are various require ments for timing relationships among the function pins, in compliance with the ata/atapi-6 specification, and these requirements are configurable by the ata module registers. 4.7.17.1 general timing requirements table 64 and figure 72 define the ac characteristics of the interface signals on all data transfer modes. figure 72. ata interface signals timing diagram 4.7.17.2 ata electrical specifications (ata bus, bus buffers) this section discusses ata parameters. for a detaile d description, refer to the ata-6 specification. the user needs to use level shifters for 3.3-v or 5.0-v compatibility on the ata interface. the use of bus buffers introduces delay on the bus and introduces skew between signal lines. these factors make it difficult to operate the bus at the highest speed (udma-5) when bus buffers are used. if fast udma mode operation is needed, this may not be compatible with bus buffers. another area of attention is the slew rate limit imposed by the ata specification on the ata bus. according to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 v/ns with a 40 pf load. few vendors of bus buffers specify slew rate of the outgoing signals. when bus buffers are used, the ata_data bus buffer is special. this is a bidirectional bus buffer, so a direction control signal is needed. this direction cont rol signal is ata_buffer_en. when it is high, the bus should drive from host to device. when it is low, the bus should drive from device to host. steering of the signal is such that contention on the host a nd device tri-state buses is always avoided. table 64. ac characteristics of all interface signals id parameter symbol min. max. unit si1 rising edge slew rate for any signal on the ata interface 1 1 srise and sfall meet this requirement when measured at the sender?s connector from 10?90% of full signal amplitude with all capacitive loads from 15 pf through 40 pf, where all signals have the same capacitive load value. s rise 1 ? 1.25 v/ns si2 falling edge slew rate for any signal on the ata interface 1 s fall 1 ? 1.25 v/ns si3 host interface signal capacitance at the host connector c host ?20pf ata interface signals si1 si2
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 99 4.7.17.3 timing parameters in the timing equations, some timing parameters are used. these parameters depend on the implementation of the ata interface on silicon, the bus buffer used, the cable delay, and the cable skew. table 65 shows ata timing parameters. table 65. ata timing parameters name description value/ contributing factor 1 1 values provided where applicable. t bus clock period (ipg_clk_ata) peripheral clock frequency ti_ds set-up time ata_data to ata_iordy edge (udma-in only) udma0 udma1 udma2, udma3 udma4 udma5 15 ns 10 ns 7 ns 5 ns 4 ns ti_dh hold time ata_iordy edge to ata_data (udma-in only) udma0, udma1, udma2, udma3, udma4 udma5 5.0 ns 4.6 ns tco propagation delay bus clock l-to-h to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en 12.0 ns tsu set-up time ata_data to bus clock l-to-h 8.5 ns tsui set-up time ata_iordy to bus clock h-to-l 8.5 ns thi hold time ata_iordy to bus clock h to l 2.5 ns tskew1 max. difference in propagation delay bus clock l-to-h to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en 7ns tskew2 max. difference in buffer propagation delay for any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en transceiver tskew3 max. difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read) transceiver tbuf max. buffer propagation delay transceiver tcable1 cable propagation delay for ata_data cable tcable2 cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack cable tskew4 max. difference in cable propagation delay between ata_iordy and ata_data (read) cable tskew5 max. difference in cable propagation delay between ( ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) cable tskew6 max. difference in cable propagation delay without accounting for ground bounce cable
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 100 4.7.17.4 pio mode timing figure 73 shows timing for pio read, and table 66 lists the timing parameters for pio read. figure 73. pio read timing diagram table 66. pio read timing parameters ata parameter parameter from figure 73 value controlling variable t1 t1 t1 (min.) = time_1 * t - (tskew1 + tskew2 + tskew5) time_1 t2 t2r t2 min.) = time_2r * t - (tskew1 + tskew2 + tskew5) time_2r t9 t9 t9 (min.) = time_9 * t - (tskew1 + tskew2 + tskew6) time_3 t5 t5 t5 (min.) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 if not met, increase time_2 t6 t6 0 ? ta ta ta (min.) = (1.5 + time_ax) * t - (tco + tsui + tcable2 + tcable2 + 2*tbuf) time_ax trd trd1 trd1 (max.) = (?trd) + (tskew3 + tskew4) trd1 (min.) = (time_pio_rdx ? 0.5)*t ? (tsu + thi) (time_pio_rdx ? 0.5) * t > tsu + thi + tskew3 + tskew4 time_pio_rdx t0 ? t0 (min.) = (time_1 + time_2 + time_9) * t time_1, time_2r, time_9
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 101 figure 74 shows timing for pio write, and table 67 lists the timing parameters for pio write. figure 74. pio write timing diagram table 67. pio write timing parameters ata parameter parameter from figure 74 value controlling variable t1 t1 t1 (min.) = time_1 * t ? (tskew1 + tskew2 + tskew5) time_1 t2 t2w t2 (min.) = time_2w * t ? (tskew1 + tskew2 + tskew5) time_2w t9 t9 t9 (min.) = time_9 * t ? (tskew1 + tskew2 + tskew6) time_9 t3 ? t3 (min.) = (time_2w ? time_on)* t ? (tskew1 + tskew2 +tskew5) if not met, increase time_2w t4 t4 t4 (min.) = time_4 * t ? tskew1 time_4 ta ta ta = (1.5 + time_ax) * t ? (tco + tsui + tcable2 + tcable2 + 2*tbuf) time_ax t0 ? t0(min.) = (time_1 + time_2 + time_9) * t time_1, time_2r, time_9 ? ? avoid bus contention when switching buffer on by making ton long enough. ? ? ? avoid bus contention when switching buffer off by making toff long enough. ?
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 102 figure 75 shows timing for mdma read, figure 76 shows timing for mdma write, and table 68 lists the timing parameters for mdma read and write. figure 75. mdma read timing diagram figure 76. mdma write timing diagram table 68. mdma read and write timing parameters ata parameter parameter from figure 75 , figure 76 value controlling variable tm, ti tm tm (min.) = ti (min.) = time_m * t ? (tskew1 + tskew2 + tskew5) time_m td td, td1 td1.(min.) = td (min.) = time_d * t ? (tskew1 + tskew2 + tskew6) time_d tk tk tk.(min.) = time_k * t ? (tskew1 + tskew2 + tskew6) time_k t0 ? t0 (min.) = (time_d + time_k) * t time_d, time_k tg(read) tgr tgr (min.-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr.(min.-drive) = td ? te(drive) time_d tf(read) tfr tfr (min.-drive) = 0 ? tg(write) ? tg (min.-write) = time_d * t ? (tskew1 + tskew2 + tskew5) time_d tf(write) ? tf (min.-write) = time_k * t ? (tskew1 + tskew2 + tskew6) time_k tl ? tl (max.) = (time_d + time_k?2)*t ? (tsu + tco + 2*tbuf + 2*tcable2) time_d, time_k
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 103 4.7.17.5 udma-in timing figure 77 shows timing when the udma-in transfer starts, figure 78 shows timing when the udma-in host terminates transfer, figure 79 shows timing when the udma-in device terminates transfer, and table 69 lists the timing parameters for the udma-in burst. figure 77. udma-in transfer starts timing diagram figure 78. udma-in host terminates transfer timing diagram tn, tj tkjn tn= tj= tkjn = (max.(time_k,. time_jn) * t ? (tskew1 + tskew2 + tskew6) time_jn ?ton toff ton = time_on * t ? tskew1 toff = time_off * t ? tskew1 ? table 68. mdma read and write timing parameters (continued) ata parameter parameter from figure 75 , figure 76 value controlling variable
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 104 figure 79. udma-in device terminates transfer timing diagram table 69. udma-in burst timing parameters ata parameter parameter from figure 77 , figure 78 , figure 79 description controlling variable tack tack tack (min.) = (time_ack * t) ? (tskew1 + tskew2) time_ack tenv tenv tenv (min.) = (time_env * t) ? (tskew1 + tskew2) tenv (max.) = (time_env * t) + (tskew1 + tskew2) time_env tds tds1 tds ? (tskew3) ? ti_ds > 0 tskew3, ti_ds, ti_dh should be low enough tdh tdh1 tdh ? (tskew3) ?ti_dh > 0 tcyc tc1 (tcyc ? tskew) > t t big enough trp trp trp (min.) = time_rp * t ? (tskew1 + tskew2 + tskew6) time_rp ?tx1 1 1 there is a special timing requirement in the ata host that requires the internal diow to go only high 3 clocks after the last active edge on the dstrobe signal. the equation given on this line tries to capture this constraint. 2. make ton and toff big enough to avoid bus contention. (time_rp * t) ? (tco + tsu + 3t + 2 *tbuf + 2*tcable2) > trfs (drive) time_rp tmli tmli1 tmli1 (min.) = (time_mlix + 0.4) * t time_mlix tzah tzah tzah (min.) = (time_zah + 0.4) * t time_zah tdzfs tdzfs tdzfs = (time_dzfs * t) ? (tskew1 + tskew2) time_dzfs tcvh tcvh tcvh = (time_cvh *t) ? (tskew1 + tskew2) time_cvh ?ton toff ton = time_on * t ? tskew1 toff = time_off * t ? tskew1 ?
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 105 4.7.17.6 udma-out timing figure 80 shows timing when the udma-out transfer starts, figure 81 shows timing when the udma-out host terminates transfer, figure 82 shows timing when the udma-out device terminates transfer, and table 70 lists the timing parameters for the udma-out burst. figure 80. udma-out transfer starts timing diagram figure 81. udma-out host terminates transfer timing diagram
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 106 figure 82. udma-out device terminates transfer timing diagram table 70. udma-out burst timing parameters ata parameter parameter from figure 80 , figure 81 , figure 82 value controlling variable tack tack tack (min.) = (time_ack * t) ? (tskew1 + tskew2) time_ack tenv tenv tenv (min.) = (time_env * t) ? (tskew1 + tskew2) tenv (max.) = (time_env * t) + (tskew1 + tskew2) time_env tdvs tdvs tdvs = (time_dvs * t) ? (tskew1 + tskew2) time_dvs tdvh tdvh tdvs = (time_dvh * t) ? (tskew1 + tskew2) time_dvh tcyc tcyc tcyc = time_cyc * t ? (tskew1 + tskew2) time_cyc t2cyc ? t2cyc = time_cyc * 2 * t time_cyc trfs1 trfs trfs = 1.6 * t + tsui + tco + tbuf + tbuf ? ? tdzfs tdzfs = time_dzfs * t ? (tskew1) time_dzfs tss tss tss = time_ss * t ? (tskew1 + tskew2) time_ss tmli tdzfs_mli tdzfs_mli =max. (time_dzfs, time_mli) * t ? (tskew1 + tskew2) ? tli tli1 tli1 > 0 ? tli tli2 tli2 > 0 ? tli tli3 tli3 > 0 ? tcvh tcvh tcvh = (time_cvh *t) ? (tskew1 + tskew2) time_cvh ?ton toff ton = time_on * t ? tskew1 toff = time_off * t ? tskew1 ?
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 107 4.7.18 parallel interface (ulpi) timing electrical and timing specifications of the parallel interface are presented in the subsequent sections. figure 83. usb transmit/receive waveform in parallel mode 4.7.19 pwm electrical specifications this section describes the electrical information of the pwm. the pwm can be programmed to select one of three clock signals as its source frequency. the se lected clock signal is passed through a prescaler before table 71. signal definitions?parallel interface name direction signal description usb_clk in interface clock. all interface signals are synchronous to the clock. usb_data[7:0] i/o bidirectional data bus, driven low by the link during idle. bus ownership is determined by dir. usb_dir in direction. control the direction of the data bus. usb_stp out stop. the link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. usb_nxt in next. the phy asserts this signal to throttle the data. table 72. usb timing specification in vp_vm unidirectional mode id parameter min. max. unit conditions / reference signal us15 usb_txoe_b ? 6.0 ns 10 pf us16 usb_dat_vp ? 0.0 ns 10 pf us17 usb_se0_vm ? 9.0 ns 10 pf usb_dir/nxt usb_stp us17 us16 usb_data us15 us16 us15 us17 usb_clk
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 108 being input to the counter. the output is available at the pulse-width modulator output (pwmo) external pin. the modulated signal of the module is observed at this pin. it can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the pwm. the smallest period is two ipg_clk periods with duty cycle of 50 percent. 4.7.20 sjc electrical specifications this section details the electrical characteristics for the sjc module. figure 84 depicts the sjc test clock input timing. figure 85 depicts the sjc boundary scan timing, figure 86 depicts the sjc test access port, figure 87 depicts the sjc trst timing, and table 73 lists the sjc timing parameters. figure 84. test clock input timing diagram figure 85. boundary scan (jtag) timing diagram tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3 tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 109 figure 86. test access port timing diagram figure 87. trst timing diagram table 73. sjc timing parameters id parameter all frequencies unit min. max. sj1 tck cycle time 100 1 ?ns sj2 tck clock pulse width measured at v m 2 40 ? ns sj3 tck rise and fall times ? 3 ns sj4 boundary scan input data set-up time 10 ? ns sj5 boundary scan input data hold time 50 ? ns sj6 tck low to output data valid ? 50 ns sj7 tck low to output high impedance ? 50 ns sj8 tms, tdi data set-up time 10 ? ns sj9 tms, tdi data hold time 50 ? ns sj10 tck low to tdo data valid ? 44 ns tck (input) tdi (input) tdo (output) tdo (output) tdo (output) vih vil input data valid output data valid output data valid tms sj8 sj9 sj10 sj11 sj10 tck (input) trst (input) sj13 sj12
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 110 4.7.21 spdif timing as spdif data is sent using biphase marking code. when encoding, the spdif data signal is modulated to the clock that is twice the bitrate of the data signal. figure 88 shows the srck timing, when spdif works in the rx mode, where srck stands for the modulating rx clock. figure 89 shows the stclk timing when spdif works in the tx mode, where stclk stands for the modulating tx clock. sj11 tck low to tdo high impedance ? 44 ns sj12 trst assert time 100 ? ns sj13 trst set-up time to tck low 40 ? ns 1 on cases where sdma tap is put in the chain, the max. tck frequency is limited by max. ratio of 1:8 of sdma core frequency to tck limitation. this implies max. frequency of 8.25 mhz (or 121.2 ns) for 66 mhz ipg clock. 2 v m - mid point voltage table 74. spdif timing characteristics symbol all frequency unit min. max. spdifin skew: asynchronous inputs, no specs apply ? ? 0.7 ns spdifout output (load = 50pf) ?skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 24.2 31.3 ns spdifout1 output (load = 30pf) ?skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 13.6 18.0 ns srck period srckp 40.0 ? ns srck high period srckph 16.0 ? ns srck low period srckpl 16.0 ? ns stclk period stclkp 40.0 ? ns stclk high period stclkph 16.0 ? ns stclk low period stclkpl 16.0 ? ns table 73. sjc timing parameters (continued) id parameter all frequencies unit min. max.
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 111 figure 88. srck timing figure 89. stclk timing 4.7.22 ssi electrical specifications this section describes the electrical information of ssi. note the following pertaining to timing information: ? all of the timing for the ssi is given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timing is on audmux signals when ssi is being used for data transfer. ? ?tx? and ?rx? refer to the transmit and receive sections of the ssi. ? for internal frame sync operation using the external clock, the fs timing will be the same as that of tx data (for example, during ac97 mode of operation). srck (output) v m v m srckp srckph srckpl stclk (input) v m v m stclkp stclkph stclkpl
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 112 4.7.22.1 ssi transmitter timing with internal clock figure 90 depicts the ssi transmitter timing with internal clock, and table 75 lists the timing parameters. figure 90. ssi transmitter with internal clock timing diagram ss19 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ss1 ad1_txd ad1_rxd ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss43 ss42 note: srxd input in synchronous mode only (output) (output) (output) (output) (input) ss19 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) ss1 dam1_txd dam1_rxd ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss42 note: srxd input in synchronous mode only (output) (output) (output) (output) (input) ss43
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 113 table 75. ssi transmitter with internal clock timing parameters id parameter min. max. unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6 ns ss6 (tx) ck high to fs (bl) high ? 15.0 ns ss8 (tx) ck high to fs (bl) low ? 15.0 ns ss10 (tx) ck high to fs (wl) high ? 15.0 ns ss12 (tx) ck high to fs (wl) low ? 15.0 ns ss14 (tx/rx) internal fs rise time ? 6 ns ss15 (tx/rx) internal fs fall time ? 6 ns ss16 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss17 (tx) ck high to stxd high/low ? 15.0 ns ss18 (tx) ck high to stxd high impedance ? 15.0 ns ss19 stxd rise/fall time ? 6 ns synchronous internal clock operation ss42 srxd setup before (tx) ck falling 10.0 ? ns ss43 srxd hold after (tx) ck falling 0 ? ns ss52 loading ? 25 pf
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 114 4.7.22.2 ssi receiver timing with internal clock figure 91 depicts the ssi receiver timing with internal clock, and table 76 lists the timing parameters. figure 91. ssi receiver with internal clock timing diagram ss50 ss48 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ad1_rxd ad1_rxc ss1 ss4 ss2 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 (output) (output) (output) (input) (output) ss3 ss5 ss50 ss48 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) dam1_rxd dam1_r_clk ss3 ss1 ss4 ss2 ss5 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 (output) (output) (output) (input) (output)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 115 table 76. ssi receiver with internal clock timing parameters id parameter min. max. unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6 ns ss7 (rx) ck high to fs (bl) high ? 15.0 ns ss9 (rx) ck high to fs (bl) low ? 15.0 ns ss11 (rx) ck high to fs (wl) high ? 15.0 ns ss13 (rx) ck high to fs (wl) low ? 15.0 ns ss20 srxd setup time before (rx) ck low 10.0 ? ns ss21 srxd hold time after (rx) ck low 0 ? ns oversampling clock operation ss47 oversampling clock period 15.04 ? ns ss48 oversampling clock high period 6 ? ns ss49 oversampling clock rise time ? 3 ns ss50 oversampling clock low period 6 ? ns ss51 oversampling clock fall time ? 3 ns
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 116 4.7.22.3 ssi transmitter timing with external clock figure 92 depicts the ssi transmitter timing with external clock, and table 77 lists the timing parameters. figure 92. ssi transmitter with external clock timing diagram ss45 ss33 ss24 ss26 ss25 ss23 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ad1_txd ad1_rxd note: srxd input in synchronous mode only ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 (input) (input) (input) (output) (input) ss45 ss33 ss24 ss26 ss25 ss23 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) dam1_txd dam1_rxd note: srxd input in synchronous mode only ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 (input) (input) (input) (output) (input)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 117 table 77. ssi transmitter with external clock timing parameters id parameter min. max. unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36.0 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36.0 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss27 (tx) ck high to fs (bl) high ?10.0 15.0 ns ss29 (tx) ck high to fs (bl) low 10.0 ? ns ss31 (tx) ck high to fs (wl) high ?10.0 15.0 ns ss33 (tx) ck high to fs (wl) low 10.0 ? ns ss37 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss38 (tx) ck high to stxd high/low ? 15.0 ns ss39 (tx) ck high to stxd high impedance ? 15.0 ns synchronous external clock operation ss44 srxd setup before (tx) ck falling 10.0 ? ns ss45 srxd hold after (tx) ck falling 2.0 ? ns ss46 srxd rise/fall time ? 6.0 ns
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 118 4.7.22.4 ssi receiver timing with external clock figure 93 depicts the ssi receiver timing with external clock, and table 78 lists the timing parameters. figure 93. ssi receiver with external clock timing diagram table 78. ssi receiver with external clock timing parameters id parameter min. max. unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36.0 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ad1_rxd ss40 ss22 ss32 ss36 ss41 (input) (input) (input) (input) ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) dam1_rxd ss40 ss22 ss32 ss36 ss41 (input) (input) (input) (input)
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 119 4.7.23 uart electrical this section describes the electrical information of the uart module. 4.7.23.1 uart rs-232 serial mode timing 4.7.23.1.14 uart transmitter figure 94 depicts the transmit timing of uart in rs-232 serial mode, with 8 data bit/1 stop bit format. table 79 lists the uart rs-232 serial mode transmit timing characteristics. figure 94. uart rs-232 serial mode transmit timing diagram ss25 (tx/rx) ck clock low period 36.0 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss28 (rx) ck high to fs (bl) high ?10.0 15.0 ns ss30 (rx) ck high to fs (bl) low 10.0 ? ns ss32 (rx) ck high to fs (wl) high ?10.0 15.0 ns ss34 (rx) ck high to fs (wl) low 10.0 ? ns ss35 (tx/rx) external fs rise time ? 6.0 ns ss36 (tx/rx) external fs fall time ? 6.0 ns ss40 srxd setup time before (rx) ck low 10.0 ? ns ss41 srxd hold time after (rx) ck low 2.0 ? ns table 78. ssi receiver with external clock timing parameters (continued) id parameter min. max. unit bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 txd (output) bit 3 start bit stop bit next start bit possible parity bit par bit ua1 ua1 ua1 ua1
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 120 4.7.23.1.15 uart receiver figure 95 depicts the rs-232 serial mode receive timing, with 8 data bit/1 stop bit format. table 80 lists serial mode receive timing characteristics. figure 95. uart rs-232 serial mode receive timing diagram 4.7.23.2 uart irda mode timing the following subsections give the uart transmit and receive timings in irda mode. 4.7.23.2.16 uart irda mode transmitter figure 96 depicts the uart irda mode transmit timing, with 8 data bit/1 stop bit format. table 81 lists the transmit timing characteristics. table 79. rs-232 serial mode transmit timing parameters id parameter symbol min. max. units ua1 transmit bit time t tbit 1/f baud_rate 1 - t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk - table 80. rs-232 serial mode receive timing parameters id parameter symbol min. max. units ua2 receive bit time 1 1 note: the uart receiver can tolerate 1/(16*f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16*f baud_rate ). t rbit 1/f baud_rate 2 - 1/(16*f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate + 1/(16*f baud_rate ) - bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rxd (input) bit 3 start bit stop bit next start bit possible parity bit par bit ua2 ua2 ua2 ua2
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 121 figure 96. uart irda mode transmit timing diagram 4.7.23.2.17 uart irda mode receiver figure 97 depicts the uart irda mode receive timing, with 8 data bit/1 stop bit format. table 82 lists the receive timing characteristics. figure 97. uart irda mode receive timing diagram table 81. irda mode transmit timing parameters id parameter symbol min. max. units ua3 transmit bit time in irda mode t tirbit 1/f baud_rate 1 - t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk - ua4 transmit ir pulse duration t tirpulse (3/16)*(1/f baud_rate ) - t ref_clk (3/16)*(1/f baud_rate ) + t ref_clk - bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 txd (output) bit 3 start bit stop bit possible parity bit ua3 ua3 ua3 ua3 ua4 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rxd (input) bit 3 start bit stop bit possible parity bit ua5 ua5 ua5 ua5 ua6
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 122 4.7.24 usb electrical specifications in order to support four different serial interfaces, the usb serial transceiver can be configured to operate in one of four modes: ? dat_se0 bidirectional, 3-wire mode ? dat_se0 unidirectional, 6-wire mode ? vp_vm bidirectional, 4-wire mode ? vp_vm unidirectional, 6-wire mode 4.7.24.1 dat_se0 bidirectional mode table 82. irda mode receive timing parameters id parameter symbol min. max. units ua5 receive bit time 1 in irda mode 1 note: the uart receiver can tolerate 1/(16*f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16*f baud_rate ). t rirbit 1/f baud_rate 2 - 1/(16*f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate + 1/(16*f baud_rate ) - ua6 receive ir pulse duration t rirpulse 1.41 us (5/16)*(1/f baud_rate )- table 83. signal definitions - dat_se0 bidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out in tx data when usb_txoe_b is low differential rx data when usb_txoe_b is high usb_se0_vm out in se0 drive when usb_txoe_b is low se0 rx indicator when usb_txoe_b is high
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 123 figure 98. usb transmit waveform in dat_se0 bidirectional mode figure 99. usb receive waveform in dat_se0 bidirectional mode table 84. signal definitions?dat_se0 bidirectional mode no. parameter signal name direction min. max. unit conditions / reference signal us1 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us2 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us3 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us4 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us7 rx rise/fall time usb_dat_vp in ? 3.0 ns 35 pf us8 rx rise/fall time usb_se0_vm in ? 3.0 ns 35 pf usb_dat_vp usb_se0_vm us1 us2 transmit us4 usb_txoe_b us3 us8 us7 usb_dat_vp usb_txoe_b receive usb_se0_vm
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 124 4.7.24.2 dat_se0 unidirectional mode figure 100. usb transmit waveform in dat_se0 unidirectional mode figure 101. usb receive waveform in dat_se0 unidirectional mode table 85. signal definitions - dat_se0 unidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out tx data when usb_txoe_b is low usb_se0_vm out se0 drive when usb_txoe_b is low usb_vp1 in buffered data on dp when usb_txoe_b is high usb_vm1 in buffered data on dm when usb_txoe_b is high usb_rcv in differential rx data when usb_txoe_b is high usb_dat_vp usb_se0_vm us9 us10 transmit us12 usb_txoe_b us11 us16 us15/us17 usb_vp1 usb_txoe_b receive usb_vm1 usb_rcv
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 125 4.7.24.3 vp_vm bidirectional mode figure 102. usb transmit waveform in vp_vm bidirectional mode table 86. usb port timing specification in dat_se0 unidirectional mode no. parameter signal name signal source min. max. unit condition / reference signal us9 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us10 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us11 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us12 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us15 rx rise/fall time usb_vp1 in ? 3.0 ns 35 pf us16 rx rise/fall time usb_vm1 in ? 3.0 ns 35 pf us17 rx rise/fall time usb_rcv in ? 3.0 ns 35 pf table 87. signal definitions?vp_vm bidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out (tx) in (rx) tx vp data when usb_txoe_b is low rx vp data when usb_txoe_b is high usb_se0_vm out (tx) in (rx) tx vm data when usb_txoe_b low rx vm data when usb_txoe_b high usb_rcv in differential rx data usb_dat_vp usb_se0_vm us18 us19 transmit usb_txoe_b us20 us22 us21 us22
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 126 figure 103. usb receive waveform in vp_vm bidirectional mode 4.7.24.4 vp_vm unidirectional mode table 88. usb port timing specification in vp_vm bidirectional mode no. parameter signal name direction min. max. unit condition / reference signal us18 tx rise/fall time usb_dat_vp out - 5.0 ns 50 pf us19 tx rise/fall time usb_se0_vm out - 5.0 ns 50 pf us20 tx rise/fall time usb_txoe_b out - 5.0 ns 50 pf us21 tx duty cycle usb_dat_vp out 49.0 51.0 % - us22 tx overlap usb_se0_vm out -3.0 +3.0 ns usb_dat_vp us26 rx rise/fall time usb_dat_vp in - 3.0 ns 35 pf us27 rx rise/fall time usb_se0_vm in - 3.0 ns 35 pf us28 rx skew usb_dat_vp in -4.0 +4.0 ns usb_se0_vm us29 rx skew usb_rcv in -6.0 +2.0 ns usb_dat_vp table 89. signal definitions?vp_vm unidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out tx vp data when usb_txoe_b is low usb_se0_vm out tx vm data when usb_txoe_b is low usb_vp1 in rx vp data when usb_txoe_b is high usb_vm1 in rx vm data when usb_txoe_b is high usb_rcv in differential rx data usb_dat_vp usb_se0_vm receive us26 us28 us27 us29 usb_rcv
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 127 figure 104. usb transmit waveform in vp_vm unidirectional mode figure 105. usb receive waveform in vp_vm unidirectional mode usb_dat_vp usb_se0_vm us30 us31 transmit usb_txoe_b us32 us34 us33 us34 us38 usb_vm1 receive usb_rcv usb_txoe_b us41 us40 us39 usb_vp1
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 128 5 package information and pinout this section includes the following: ? pin/contact assignment information ? mechanical package drawing 5.1 mapbga production package 1568-01, 17 x 17 mm, 0.8 pitch see figure 106 for the package drawing and dimensions of the production package. table 90. usb timing specification in vp_vm unidirectional mode no. parameter signal direction min. max. unit conditions / reference signal us30 tx rise/fall time usb_dat_vp out - 5.0 ns 50 pf us31 tx rise/fall time usb_se0_vm out - 5.0 ns 50 pf us32 tx rise/fall time usb_txoe_b out - 5.0 ns 50 pf us33 tx duty cycle usb_dat_vp out 49.0 51.0 % - us34 tx overlap usb_se0_vm out -3.0 +3.0 ns usb_dat_vp us38 rx rise/fall time usb_vp1 in - 3.0 ns 35 pf us39 rx rise/fall time usb_vm1 in - 3.0 ns 35 pf us40 rx skew usb_vp1 in -4.0 +4.0 ns usb_vm1 us41 rx skew usb_rcv in -6.0 +2.0 ns usb_vp1
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 129 5.2 production package outline drawing figure 106. production package: mechanical drawing
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 130 5.2.1 mapbga signal assignments table 91 lists mapbga signals al phabetized by signal name. table 92 shows the signal assignment on the mcimx35 ball map. table 91. signal ball map locations signal id ball location signal id ball location a0 a5 ata_data7 1 y3 a1 d7 ata_data8 1 u4 a10 f15 ata_data9 1 w3 a11 d5 ata_dior 1 y6 a12 f6 ata_diow 1 w6 a13 b3 ata_dmack 1 v6 a14 d14 ata_dmarq 1 t3 a15 d15 ata_intrq 1 v2 a16 d13 ata_iordy 1 u6 a17 d12 ata_reset_b 1 t6 a18 e11 bclk e14 a19 d11 boot_mode0 w10 a2 e7 boot_mode1 u9 a20 d10 capture v12 a21 e10 cas e16 a22 d9 clk_mode0 y10 a23 e9 clk_mode1 t10 a24 d8 clko v10 a25 e8 compare t12 a3 c6 contrast 1 l16 a4 d6 cs0 f17 a5 b5 cs1 e19 a6 c5 cs2 b20 a7 a4 cs3 c19 a8 b4 cs4 e18 a9 a3 cs5 f19 ata_buff_en 1 t5 csi_d10 1 v16 ata _ c s 0 1 v7 csi_d11 1 t15 ata _ c s 1 1 t7 csi_d12 1 w16 ata _ da 0 1 r4 csi_d13 1 v15 ata _ da 1 1 v1 csi_d14 1 u14 ata _ da 2 1 r5 csi_d15 1 y16 ata _ d ata 0 1 y5 csi_d8 1 u15 ata _ d ata 1 1 w5 csi_d9 1 w17 ata _ data 1 0 1 v3 csi_hsync 1 v14 ata _ data 1 1 1 y2 csi_mclk 1 w15 ata _ data 1 2 1 u3 csi_pixclk 1 y15 ata _ data 1 3 1 w2 csi_vsync 1 t14 ata _ data 1 4 1 w1 cspi1_miso v9 ata _ data 1 5 1 t4 cspi1_mosi w9 ata _ d ata 2 1 v5 cspi1_sclk w8 ata_data3 u5 cspi1_spi_rdy t8
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 131 ata_data4 y4 cspi1_ss0 y8 ata_data5 w4 cspi1_ss1 u8 ata _ data 6 v 4 c t s 1 r 3 cts2 g5 fec_tdata0 p5 d0 a2 fec_tdata1 m4 d1 d4 fec_tdata2 m5 d10 d2 fec_tdata3 l6 d11 e6 fec_tx_clk p4 d12 e3 fec_tx_en t1 d13 f5 fec_tx_err n4 d14 d1 fsr k5 d15 e2 fst j1 d2 b2 fuse_vdd p13 d3 e5 fuse_vss m11 d3_cls 1 l17 gpio1_0 t11 d3_drdy 1 l20 gpio1_1 y11 d3_fpshift 1 l15 gpio2_0 u11 d3_hsync 1 l18 gpio3_0 v11 d3_rev 1 m17 hckr k2 d3_spl 1 m18 hckt j5 d3_vsync 1 m19 i2c1_clk m20 d4 c3 i2c1_dat n17 d5 b1 i2c2_clk l3 d6 d3 i2c2_dat m1 d7 c2 lba d20 d8 c1 ld0 1 f20 d9 e4 ld1 1 g18 de_b w19 ld10 1 h20 dqm0 b19 ld11 1 j18 dqm1 d17 ld12 1 j16 dqm2 d16 ld13 1 j19 dqm3 c18 ld14 1 j17 eb0 f18 ld15 1 j20 eb1 f16 ld16 1 k14 ecb d19 ld17 1 k19 ext_armclk v8 ld18 1 k18 extal_audio w20 ld19 1 k20 extal24m t20 ld2 1 g17 fec_col p3 ld20 1 k16 fec_crs n5 ld21 1 k17 fec_mdc r1 ld22 1 k15 fec_mdio p1 ld23 1 l19 fec_rdata0 p2 ld3 1 g16 fec_rdata1 n2 ld4 1 g19 fec_rdata2 m3 ld5 1 h16 fec_rdata3 n1 ld6 1 h18 table 91. signal ball map locations (continued) signal id ball location signal id ball location
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 132 fec_rx_clk r2 ld7 1 g20 fec_rx_dv t2 ld8 1 h17 fec_rx_err n3 ld9 1 h19 ma10 c4 nvcc_emi2 g12 mgnd n11 nvcc_emi2 f13 mlb_clk w13 nvcc_emi2 f14 mlb_dat y13 nvcc_emi3 g14 mlb_sig w12 nvcc_jtag p16 mvdd p11 nvcc_lcdc h14 nf_ce0 g3 nvcc_lcdc j14 nfale f2 nvcc_lcdc l14 nfcle e1 nvcc_lcdc m14 nfrb f3 nvcc_misc k6 nfre_b f1 nvcc_misc k7 nfwe_b g2 nvcc_misc l8 nfwp_b f4 nvcc_mlb r10 ngnd_ata m9 nvcc_nfc g6 ngnd_ata p9 nvcc_nfc h6 ngnd_ata l10 nvcc_nfc h7 ngnd_crm l11 nvcc_sdio p14 ngnd_csi n10 oe e20 ngnd_emi1 h8 osc_audio_vdd v20 ngnd_emi1 h10 osc_audio_vss u19 ngnd_emi1 j10 osc24m_vdd t19 ngnd_emi2 j11 osc24m_vss t18 ngnd_emi3 j12 pgnd m12 ngnd_emi3 k12 phy1_vdda m15 ngnd_jtag m13 phy1_vdda n20 ngnd_lcdc k11 phy1_vssa n16 ngnd_lcdc l12 phy1_vssa p20 ngnd_misc m7 phy2_vdd r13 ngnd_misc k8 phy2_vss p12 ngnd_mlb m10 por_b w11 ngnd_nfc k9 power_fail y9 ngnd_sdio n12 pvdd n13 nvcc_ata n6 ras e15 nvcc_ata p6 reset_in_b u10 nvcc_ata p7 rtck u18 nvcc_ata p8 rts1 u1 nvcc_crm r9 rts2 g1 nvcc_csi r11 rw c20 nvcc_emi1 g7 rxd1 u2 nvcc_emi1 g8 rxd2 h3 nvcc_emi1 g9 sck4 l4 nvcc_emi1 h9 sck5 l5 nvcc_emi1 f10 sckr k3 table 91. signal ball map locations (continued) signal id ball location signal id ball location
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 133 nvcc_emi1 g10 sckt j4 nvcc_emi1 f11 sd0 c17 nvcc_emi1 g11 sd1 a19 sd1_clk v18 sdclk e12 sd1_cmd y19 sdclk_b e13 sd1_data0 r14 sdqs0 b17 sd1_data1 u16 sdqs1 a13 sd1_data2 w18 sdqs2 a10 sd1_data3 v17 sdqs3 c7 sd10 a15 sdwe g15 sd11 b15 sjc_mod u17 sd12 c13 srxd4 l1 sd13 b14 srxd5 k4 sd14 a14 stxd4 m2 sd15 b13 stxd5 k1 sd16 c12 stxfs4 l2 sd17 c11 stxfs5 j6 sd18 a12 tck r17 sd19 b12 tdi p15 sd2 b18 tdo r15 sd2_clk w14 test_mode y7 sd2_cmd u13 tms r16 sd2_data0 v13 trstb t16 sd2_data1 t13 ttm_pad m16 sd2_data2 y14 tx0 g4 sd2_data3 u12 tx1 h1 sd20 b11 tx2_rx3 h5 sd21 a11 tx3_rx2 j2 sd22 c10 tx4_rx1 h4 sd23 b10 tx5_rx0 j3 sd24 a9 txd1 r6 sd25 c9 txd2 h2 sd26 b9 usbotg_oc u7 sd27 a8 usbotg_pwr w7 sd28 b8 usbphy1_dm n19 sd29 c8 usbphy1_dp p19 sd3 c16 usbphy1_rref r19 sd30 a7 usbphy1_uid n18 sd31 b7 usbphy1_upllgnd n14 sd4 a18 usbphy1_upllvdd n15 sd5 c15 usbphy1_upllvdd p17 sd6 a17 usbphy1_vbus p18 sd7 b16 usbphy1_vdda_bias r20 sd8 c14 usbphy1_vssa_bias r18 sd9 a16 usbphy2_dm y17 sdba0 a6 usbphy2_dp y18 table 91. signal ball map locations (continued) signal id ball location signal id ball location
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 134 sdba1 b6 vdd m6 sdcke0 d18 vdd f7 sdcke1 e17 vdd j7 vdd l7 vss l9 vdd n7 vss n9 vdd r7 vss k10 vdd f8 vss p10 vdd r8 vss h11 vdd f9 vss h12 vdd f12 vss h13 vdd r12 vss j13 vdd g13 vss k13 vdd h15 vss l13 vdd j15 vss t17 vss a1 vss a20 vss y1 vss y20 vss j8 vstby t9 vss m8 wdog_rst y12 vss n8 xtal_audio v19 vss j9 xtal24m u20 1 not available for the mcimx351. table 91. signal ball map locations (continued) signal id ball location signal id ball location
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 135 table 92. ball map?17 x 17, 0.8 mm pitch 1 1 see ta b l e 9 1 for pins unavailable in the mcimx351 soc. 1 2 3 4 5 6 7 8 9 1011121314151617181920 a vss d0 a9 a7 a0 sdba 0 sd30 sd27 sd24 sdq s2 sd21 sd18 sdq s1 sd14 sd10 sd9 sd6 sd4 sd1 vss a b d5 d2 a13 a8 a5 sdba 1 sd31 sd28 sd26 sd23 sd20 sd19 sd15 sd13 sd11 sd7 sdq s0 sd2 dqm 0 cs2 b cd8d7d4ma10a6a3sdq s3 sd29 sd25 sd22 sd17 sd16 sd12 sd8 sd5 sd3 sd0 dqm 3 cs3 rw c d d14 d10 d6 d1 a11 a4 a1 a24 a22 a20 a19 a17 a16 a14 a15 dqm 2 dqm 1 sdck e0 ecb lba d enfcl e d15 d12 d9 d3 d11 a2 a25 a23 a21 a18 sdcl k sdcl k_b bclk ras cas sdck e1 cs4 cs1 oe e fnfre _b nfal e nfrb nfw p_b d13 a12 vdd vdd vdd nvc c_em i1 nvc c_em i1 vdd nvc c_em i2 nvc c_em i2 a10 eb1 cs0 eb0 cs5 ld0 f g rts2 nfw e_b nf_c e0 tx0 cts2 nvc c_nf c nvc c_em i1 nvc c_em i1 nvc c_em i1 nvc c_em i1 nvc c_em i1 nvc c_em i2 vdd nvc c_em i3 sdw e ld3 ld2 ld1 ld4 ld7 g h tx1 txd2 rxd2 tx4_ rx1 tx2_ rx3 nvc c_nf c nvc c_nf c ngn d_em i1 nvc c_em i1 ngn d_em i1 vss vss vss nvc c_lc dc vdd ld5 ld8 ld6 ld9 ld10 h jfsttx3_ rx2 tx5_ rx0 sckt hckt stxf s5 vdd vss vss ngn d_em i1 ngn d_em i2 ngn d_em i3 vss nvc c_lc dc vdd ld12 ld14 ld11 ld13 ld15 j kstxd 5 hck r sckr srxd 5 fsr nvc c_mi sc nvc c_mi sc ngn d_mi sc ngn d_nf c vss ngn d_lc dc ngn d_em i3 vss ld16 ld22 ld20 ld21 ld18 ld17 ld19 k lsrxd 4 stxf s4 i2c2_ clk sck4 sck5 fec_ tdat a3 vdd nvc c_mi sc vss ngn d_at a ngn d_cr m ngn d_lc dc vss nvc c_lc dc d3_f pshi ft con tras t d3_c ls d3_h sync ld23 d3_d rdy l mi2c2_ dat stxd 4 fec_ rdat a2 fec_ tdat a1 fec_ tdat a2 vdd ngn d_mi sc vss ngn d_at a ngn d_ml b fuse _vss pgn d ngn d_jt ag nvc c_lc dc phy1 _vdd a ttm_ pa d d3_r ev d3_s pl d3_v sync i2c1_ clk m nfec_ rdat a3 fec_ rdat a1 fec_ rx_e rr fec_ tx_e rr fec_ crs nvc c_at a vdd vss vss ngn d_cs i mgn d ngn d_sd io pvdd usbp hy1_ upll gnd usbp hy1_ upll vdd phy1 _vss a i2c1_ dat usbp hy1_ uid usbp hy1_ dm phy1 _vdd a n pfec_ mdio fec_ rdat a0 fec_ col fec_ tx_c lk fec_ tdat a0 nvc c_at a nvc c_at a nvc c_at a ngn d_at a vss mvd d phy2 _vss fuse _vdd nvc c_sd io tdi nvc c_jt ag usbp hy1_ upll vdd usbp hy1_ vbus usbp hy1_ dp phy1 _vss a p rfec_ mdc fec_ rx_c lk cts1 ata_ da0 ata _ da2 txd1 vdd vdd nvc c_cr m nvc c_ml b nvc c_cs i vdd phy2 _vdd sd1_ data 0 tdo tms tck usbp hy1_ vssa _bia s usbp hy1_ rref usbp hy1_ vdda _bia s r tfec_ tx_e n fec_ rx_d v ata _ dma rq ata _ data 15 ata _ buff _en ata _ rese t_b ata _ cs1 cspi 1_spi _rdy vstb y clk_ mod e1 gpio 1_0 com pa r e sd2_ data 1 csi_ vsyn c csi_ d11 trst b vss osc2 4m_v ss osc2 4m_v dd exta l24m t urts1rxd1ata_ data 12 ata _ data 8 ata _ data 3 ata _ i ordy usb otg_ oc cspi 1_ss 1 boot _mo de1 rese t_in_ b gpio 2_0 sd2_ data 3 sd2_ cmd csi_ d14 csi_ d8 sd1_ data 1 sjc_ mod rtck osc_ audi o_vs s xtal 24m u vata_ da1 ata _ i ntr q ata _ data 10 ata _ data 6 ata _ data 2 ata _ dma ck ata _ cs0 ext_ arm clk cspi 1_mi so clko gpio 3_0 capt ure sd2_ data 0 csi_ hsyn c csi_ d13 csi_ d10 sd1_ data 3 sd1_ clk xtal _aud io osc_ audi o_vd d v wata_ data 14 ata _ data 13 ata _ data 9 ata _ data 5 ata _ data 1 ata _ diow usb otg_ pwr cspi 1_sc lk cspi 1_mo si boot _mo de0 por_ b mlb_ sig mlb_ clk sd2_ clk csi_ mclk csi_ d12 csi_ d9 sd1_ data 2 de_b exta l_au dio w yvssata_ data 11 ata _ data 7 ata _ data 4 ata _ data 0 ata _ dior test _mo de cspi 1_ss 0 pow er_f ail clk_ mod e0 gpio 1_1 wdo g_rs t mlb_ dat sd2_ data 2 csi_ pixc lk csi_ d15 usbp hy2_ dm usbp hy2_ dp sd1_ cmd vss y
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 136 6 product documentation all related product documenta tion for the i.mx35 processor is located at http://www.freescale.com/imx. 7 revision history table 93 shows the revision history of this document. table 93. mcimx35 data sheet revision history revision number date substantive change(s) 1 12/2008 ? section 4.3.1, ?powering up? : in the power-up sequence, inserted the step, ?wait 32 s,? after step 2, and inserted as the second-to-last step, ?wait 100 s.? ? section 4.7, ?module-level ac electrical specifications? : updated nfc, sdram and mddr sdram timing. inserted ddr2 sdram timing. 0 10/2008 initial public release
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mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 138 this page intentionally left blank
mcimx35 (i.mx35) multimedia applications processor for automotive products advance information, rev. 1 preliminary?subject to change without notice freescale semiconductor 139 this page intentionally left blank
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